Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Abstract: A method for authorizing an access to a table of address correspondence between a multitask CPU and at least one memory containing several programs, consisting of calculating, on each task change of the CPU, a signature of at least part of the program instruction lines, and checking the conformity of this signature with a signature recorded upon previous execution of the involved program.

Abstract: A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

Abstract: A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.

Abstract: A method and a system of access control between a main processor and peripherals connected by a communication bus, including assigning, to all or part of the programs to be executed by the main processor, at least one token selectively authorizing access to one or several of said peripherals, said token being provided at least initially by an auxiliary processor exploiting a memory distinct from that of the main processor; and checking, for each request of access of one of said programs to one of said peripherals, the presence of said authorization token for the access to the concerned peripheral.

Abstract: A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

Abstract: A method of cyphering, by an integrated processor, of a set of data to be stored in a memory, including performing, in a continuous operation following a data flow, the steps of dividing the data flow into blocks of predetermined size and, for each block: generating a cyphering key using a pseudo-random generator implementing a continuous algorithm of cyphering according to a key specific to the integrated circuit and of an initialization vector changing for each block; combining the data block and the corresponding key in a continuous operation; and storing in the memory each cyphered block and the initialization vector used to cypher it.

Abstract: A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.

Abstract: A method and a system of access control between a main processor and peripherals connected by a communication bus, consisting of: assigning, to all or part of the programs to be executed by the main processor, at least one token selectively authorizing access to one or several of said peripherals, said token being provided at least initially by an auxiliary processor exploiting a memory distinct from that of the main processor; and checking, for each request of access of one of said programs to one of said peripherals, the presence of said authorization token for the access to the concerned peripheral.

Abstract: A method for authorizing an access to a table of address correspondence between a multitask CPU and at least one memory containing several programs, consisting of calculating, on each task change of the CPU, a signature of at least part of the program instruction lines, and checking the conformity of this signature with a signature recorded upon previous execution of the involved program.

Abstract: A circuit for verifying the integrity of a software code executed by a processor, comprising transferring, by blocks, the software code from a storage memory external to the processor and of executing, in parallel with the execution of the software code, an algorithm of verification of the software code by means of a dedicated circuit, separate from said processor for executing the software code.

Abstract: A method of cyphering by an integrated processor of a set of data to be stored in a memory, consisting of performing, in a continuous operation following a data flow, the steps of dividing the data flow into blocks of predetermined size and, for each block: generating a cyphering key by means of a pseudo-random generator implementing a continuous algorithm of cyphering according to a key specific to the integrated circuit and of an initialization vector changing for each block; combining the data block and the corresponding key in a continuous operation; and storing in said memory each cyphered block and the initialization vector used to cypher it.