Patents by Inventor Stephan-Detlef Kronholz

Stephan-Detlef Kronholz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8836047
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8809151
    Abstract: In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Stephan-Detlef Kronholz, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8722481
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8674458
    Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Rohit Pal, Gunda Beernink
  • Patent number: 8664066
    Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Stephan-Detlef Kronholz
  • Patent number: 8614122
    Abstract: When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Gunda Beernink, Carsten Reichel
  • Publication number: 20130267044
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Application
    Filed: June 4, 2013
    Publication date: October 10, 2013
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8536009
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Maciej Wiatr, Stephan-Detlef Kronholz
  • Patent number: 8481381
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Publication number: 20130065329
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8377786
    Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 19, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Roman Boschke
  • Publication number: 20130040430
    Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 14, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit Pal, Stephan-Detlef Kronholz
  • Patent number: 8343826
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Publication number: 20120306027
    Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef Kronholz, Rohit Pal, Gunda Beernink
  • Publication number: 20120295420
    Abstract: A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 22, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit Pal, Stephan-Detlef Kronholz
  • Publication number: 20120235245
    Abstract: When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the sensitive gate materials may be improved by reducing the depth of or eliminating recessed areas that are obtained after forming sophisticated trench isolation regions. To this end, after completing the STI module, an additional fill material may be provided so as to obtain the desired surface topography and also preserve superior material characteristics of the trench isolation regions.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit Pal, Stephan-Detlef Kronholz
  • Publication number: 20120235249
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Publication number: 20120202326
    Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 9, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef KRONHOLZ, Peter JAVORKA, Roman BOSCHKE
  • Publication number: 20120161249
    Abstract: When forming sophisticated gate electrode structures in an early manufacturing stage, the threshold voltage characteristics may be adjusted on the basis of a semiconductor alloy, which may be formed on the basis of low pressure CVD techniques. In order to obtain a desired high band gap offset, for instance with respect to a silicon/germanium alloy, a moderately high germanium concentration may be provided within the semiconductor alloy, wherein, however, at the interface formed with the semiconductor base material, a low germanium concentration may significantly reduce the probability of creating dislocation defects.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Ina Ostermay, Roman Boschke
  • Publication number: 20120161203
    Abstract: In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.
    Type: Application
    Filed: August 2, 2011
    Publication date: June 28, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Stephan-Detlef Kronholz, Jan Hoentschel, Thilo Scheiper