Patents by Inventor Stephan Diestelhorst

Stephan Diestelhorst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140040567
    Abstract: A system and method are disclosed for increasing large region transaction throughput by making informed determinations whether to abort a thread from a first core or a thread from a second core when a conflict is detected between the threads. Such a system and method allow resolution of conflicts between a first thread and a second thread. In certain embodiments, the system and method allow a requester to detect a conflict under specific circumstances and make an intelligent decision whether to abort the first thread, enter a wait state to give the first thread an opportunity to complete execution or, if possible, abort the second thread.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Martin T. Pohlack, Stephan Diestelhorst
  • Publication number: 20140040554
    Abstract: A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method include a Hardware-based Transactional Memory (HTM) mechanism that tracks meta-data such as page-table entries (PTE) rather than all the data itself. The HTM mechanism protects large regions of memory by providing conflict detection so that regions of memory can be located within a local read or write set.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Martin T. Pohlack, Stephan Diestelhorst
  • Patent number: 8621183
    Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: December 31, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael P. Hohmuth, David S. Christie, Stephan Diestelhorst
  • Patent number: 8612694
    Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Martin T. Pohlack, Michael P. Hohmuth, Stephan Diestelhorst, David S. Christie, Jaewoong Chung
  • Publication number: 20130290965
    Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 31, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Martin T. Pohlack, Stephan Diestelhorst
  • Patent number: 8543775
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 24, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S Christie, Michael Hohmuth, Stephan Diestelhorst, Martin Pohlack, Luke Yen
  • Publication number: 20130159653
    Abstract: In at least one embodiment, a method includes determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. In at least one embodiment of the method, the lock operation is associated with a first access of a shared resource and the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Martin T. Pohlack, Stephan Diestelhorst
  • Publication number: 20130159673
    Abstract: A method is provided that includes determining a number of outstanding out-of-order instructions in an instruction stream. The method includes determining a number of available hardware resources for executing out-of-order instructions and inserting fencing instructions into the instruction stream if the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. A second method is provided for compiling source code that includes determining a speculative region. The second method includes generating machine-level instructions and inserting fencing instructions into the machine-level instructions in response to determining the speculative region. A processing device is provided that includes cache memory and a processing unit to execute processing device instructions in an instruction stream.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Martin T. Pohlack, Michael Hohmuth, Stephan Diestelhorst, David Christie, Luke Yen
  • Publication number: 20130151791
    Abstract: A computing device initiates a transaction, corresponding to an application, which includes operations for accessing data stored in a shared memory and buffering alterations to the data as speculative alterations to the shared memory. The computing device detects a transaction abort scenario corresponding to the transaction and notifies the application regarding the transaction abort scenario. The computing device determines whether to abort the transaction based on instructions received from the application regarding the transaction abort scenario. When the transaction is to be aborted, the computing device restores the transaction to an operation prior to accessing the data stored in the shared memory and buffering alterations to the data as speculative alterations to the shared memory. When the transaction is not to be aborted, the computing device enables the transaction to continue.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Stephan DIESTELHORST, Martin POHLACK, Michael HOHMUTH, David CHRISTIE, Luke YEN
  • Patent number: 8407455
    Abstract: A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 26, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst
  • Patent number: 8386749
    Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: February 26, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Dannowski, Stephan Diestelhorst, Sebastian Biemueller
  • Patent number: 8352688
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen
  • Publication number: 20120233411
    Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 13, 2012
    Inventors: Martin T. Pohlack, Michael P. Hohmuth, Stephan Diestelhorst, David S. Christie, Jaewoong Chung
  • Publication number: 20120159084
    Abstract: A method is provided for identifying a first portion of a computer program for speculative execution by a first processor element. At least one memory object is declared as being protected during the speculative execution. Thereafter, if a first signal is received indicating that the at least one protected memory object is to be accessed by a second processor element, then delivery of the first signal is delayed for a preselected duration of time to potentially allow the speculative execution to complete. The speculative execution of the first portion of the computer program may be aborted in response to receiving the delayed first signal before the speculative execution of the first portion of the computer program has been completed.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: MARTIN T. POHLACK, Michael P. Hohmuth, Stephan Diestelhorst, David S. Christie, JaeWoong Chung
  • Patent number: 8195917
    Abstract: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 5, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael P. Hohmuth, Uwe M. Dannowski, Sebastian Biemueller, David S. Christie, Stephan Diestelhorst, Thomas Friebel
  • Publication number: 20120124293
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen
  • Publication number: 20120124563
    Abstract: A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Inventors: Jaewoong Chung, Rahmet Ulya Karpuzcu, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack
  • Patent number: 8127057
    Abstract: An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 28, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack
  • Publication number: 20110307689
    Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen
  • Publication number: 20110231630
    Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 22, 2011
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Uwe Dannowski, Stephan Diestelhorst, Sebastian Biemueller