Abstract: The present document relates to linear regulators or linear voltage regulators configured to provide a constant output voltage. In particular, the present document relates to driver circuits of low-dropout (LDO) regulators. A driver circuit (300) for driving a pass device (201) of a linear regulator (120) is described. The driver circuit (300) comprises a driver stage (110) adapted to regulate a driver gate (220) for connecting to the gate of the pass device (201); wherein the driver stage (110) comprises a transistor diode (210) having the driver gate (220); and a feedback transistor (305) having a source and a drain coupled to a source and drain of the transistor diode (210); wherein a feedback voltage at the gate of the feedback transistor (305) is regulated based on the output current of the pass device (201).

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: The present document relates to a current sensing and/or control circuit with reduced sensing errors. A current control circuit for controlling a load current into an electronic device is described. The current control circuit comprises an array of control transistors configured to adjust the load current provided at an output of the array of control transistors. The load current is drawn from a power supply at an input voltage. Furthermore, the power supply is coupled to an input of the array of control transistors. The circuit further comprises a reference transistor coupled to the power supply at an input of the reference transistor and a reference current source configured to draw a reference current at an output of the reference transistor.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage.

Abstract: The present document relates to linear regulators or linear voltage regulators configured to provide a constant output voltage. In particular, the present document relates to driver circuits of low-dropout (LDO) regulators. A driver circuit (300) for driving a pass device (201) of a linear regulator (120) is described. The driver circuit (300) comprises a driver stage (110) adapted to regulate a driver gate (220) for connecting to the gate of the pass device (201); wherein the driver stage (110) comprises a transistor diode (210) having the driver gate (220); and a feedback transistor (305) having a source and a drain coupled to a source and drain of the transistor diode (210); wherein a feedback voltage at the gate of the feedback transistor (305) is regulated based on the output current of the pass device (201).

Abstract: The present document relates to low-dropout (LDO) regulators having low output capacitance. The regulator comprises a differential amplification stage configured to amplify a differential voltage between a reference voltage and a measure of the output voltage, thereby yielding a drive current at an output of the amplification stage; a subsequent output amplification stage configured to provide the regulated output voltage and a output current at an output of the output amplification stage, based on a drive voltage at an input of the output amplification stage; and a first output current feedback loop configured to sense the output current; and feed back a first coupling current derived from the sensed output current to a first intermediate point between the output of the differential amplification stage and the input of the output amplification stage; wherein the drive voltage is dependent on the drive current and the first coupling current.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage.

Abstract: A system includes a transistor coupled to a voltage rail, a first resistor coupled in series with the transistor, and a second resistor coupled in series with the first resistor. The system also includes a bandgap reference circuit operable to generate a bandgap reference voltage of less than 1.2 volts (such as one volt) between the first and second resistors. The bandgap reference circuit includes a diode configured to generate a complementary-to-absolute-temperature (CTAT) voltage and a third resistor configured to generate a first proportional-to-absolute-temperature (PTAT) voltage using a first current. The bandgap reference circuit also includes a current source configured to sink a CTAT current from the first current to generate a second current and a fourth resistor configured to generate a second PTAT voltage using the second current. A sum of the CTAT voltage, the first PTAT voltage, and the second PTAT voltage is less than 1.2 volts.

Abstract: A voltage reference circuit is provided. The voltage reference circuit includes a first PTAT voltage generator and an amplifier. The first PTAT voltage generator is operable to generate a first PTAT voltage. The amplifier, which is coupled to the first PTAT voltage generator, comprises a second PTAT voltage generator that is complementary to the first PTAT voltage generator. The second PTAT voltage generator is operable to generate a second PTAT voltage. The amplifier is operable to generate a reference voltage based on the first PTAT voltage and the second PTAT voltage.

Abstract: The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor. According to the invention, it is provided that firstly, in a first step, the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. In a second step, it is provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage.

Abstract: The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor. According to the invention, it is provided that firstly, in a first step, the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. In a second step, it is provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage.