Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

Abstract: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract: A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate.

Abstract: A microprocessor includes two or more processing cores each configured to compute a first value in response to detecting a power event. The first value represents an amount of energy the core consumed during a time interval leading up to the event. The length of the time interval is predetermined. Each core reads from the memory one or more second values that represent an amount of energy the other cores consume during approximately the time interval. The second values were previously computed and written to the memory by the other cores. Each core adjusts its operating frequency based on the first and second values. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

Abstract: A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

Abstract: A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the fuses to circuits of the microprocessor to control operation thereof. A second plurality of fuses are blown with the predetermined number of the first plurality of fuses that are blown and a Boolean complement of the predetermined number. In response to being reset, the microprocessor: reads the predetermined number and the Boolean complement of the predetermined number from the second plurality of fuses, Boolean complements the predetermined number read from the second plurality of fuses to generate a result, compares the result with the Boolean complement of the predetermined number read from the second plurality of fuses, and prevent itself from fetching and executing user program instructions if the result does not equal the Boolean complement of the predetermined number read from the second plurality of fuses.

Abstract: A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses.

Abstract: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The power management unit controls the microprocessor to operate at the predetermined frequency only if the microprocessor was most recently instructed by system software to operate at a highest frequency instructable by the system software. The highest frequency instructable by the system software is less than the predetermined frequency.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software.

Abstract: A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate.

Abstract: A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

Abstract: A microprocessor includes two or more processing cores each configured to compute a first value in response to detecting a power event. The first value represents an amount of energy the core consumed during a time interval leading up to the event. The length of the time interval is predetermined. Each core reads from the memory one or more second values that represent an amount of energy the other cores consume during approximately the time interval. The second values were previously computed and written to the memory by the other cores. Each core adjusts its operating frequency based on the first and second values. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

Abstract: A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses.

Abstract: A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the fuses to circuits of the microprocessor to control operation thereof. A second plurality of fuses are blown with the predetermined number of the first plurality of fuses that are blown and a Boolean complement of the predetermined number. In response to being reset, the microprocessor: reads the predetermined number and the Boolean complement of the predetermined number from the second plurality of fuses, Boolean complements the predetermined number read from the second plurality of fuses to generate a result, compares the result with the Boolean complement of the predetermined number read from the second plurality of fuses, and prevent itself from fetching and executing user program instructions if the result does not equal the Boolean complement of the predetermined number read from the second plurality of fuses.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software.

Abstract: A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency being the maximum frequency at which the microprocessor will reliably operate at the first temperature and the first voltage. Operating point data also includes a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage, the second frequency being greater than the first frequency and the second temperature less than the first temperature. A control circuit causes the microprocessor to operate at the second voltage and frequency rather than the first voltage and frequency in response to detecting that while operating at the first voltage and the first frequency the operating temperature dropped below the second temperature.