Patents by Inventor Stephan Henneck

Stephan Henneck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for processing a semiconductor workpiece and semiconductor workpiece
    Patent number: 9627335
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stephan Henneck, Evelyn Napetschnig, Daniel Pedone, Bernhard Weidgans, Simon Faiss, Ivan Nikitin
  • SEMICONDUCTOR DEVICE HAVING A STRESS-COMPENSATED CHIP ELECTRODE
    Publication number: 20160126197
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 5, 2016
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Dirk Ahlers, Ulrike Fastner, Petra Fischer, Karl-Heinz Gasser, Stephan Henneck, Stefan Krivec, Florian Weilnboeck
  • Method for Processing a Semiconductor Workpiece and Semiconductor Workpiece
    Publication number: 20150325535
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Stephan HENNECK, Evelyn NAPETSCHNIG, Daniel PEDONE, Bernhard WEIDGANS, Simon FAISS, Ivan NIKITIN
  • Protection Layers for Conductive Pads and Methods of Formation Thereof
    Publication number: 20140319688
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky
  • Protection layers for conductive pads and methods of formation thereof
    Patent number: 8835319
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky
  • Protection Layers for Conductive Pads and Methods of Formation Thereof
    Publication number: 20130228929
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Infineon Technologies AG
    Inventors: Dirk Meinhold, Norbert Mais, Reimund Engl, Hans-Joerg Timme, Alfred Vater, Stephan Henneck, Norbert Urbansky