Patents by Inventor Stephan J. C. H. Theeuwen

Stephan J. C. H. Theeuwen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7989879
    Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Freerk Van Rijs, Stephan J. C. H. Theeuwen, Petra C. A. Hammes
  • Publication number: 20110073946
    Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a source region (10) with a source portion (73) and a drain region (12). The source portion and drain region are of a second conductivity type opposite to the first conductivity type and are mutually connected through a channel region (28) in the substrate over which a gate electrode (14) extends. The drain region comprises a drain contact region (16) and a drain extension region (15) which extends from the channel region (28) towards the drain contact region. The drain contact region is electrically connected to a top metal layer (22) by a drain contact (20), and a poly-Si drain contact layer (80) is arranged as a first contact material in between the drain contact region and the drain contact in a contact opening (51) of a first dielectric layer (52) deposited on the surface of the drain region.
    Type: Application
    Filed: May 19, 2009
    Publication date: March 31, 2011
    Applicant: NXP B.V.
    Inventors: Stephan J. C. H. Theeuwen, Henk J. Peuscher, Rene Van Den Heuvel, Paul Bron
  • Publication number: 20090218622
    Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).
    Type: Application
    Filed: July 10, 2006
    Publication date: September 3, 2009
    Applicant: NXP B.V.
    Inventors: Freerk Van Rijs, Stephan J., C., H. Theeuwen, Petra C., A. Hammes