Abstract: A system and method of fetching processor instructions provides enhanced performance. The method and system provide for receiving a request for an instruction, and searching a cache system at a first level for the instruction. The cache system is searched at a second level for the instruction in parallel with the first level based on a prediction of whether the instruction will be found at the first level.

Abstract: A method for stopping replay tornadoes in a processor. The method of one embodiment comprises scheduling an instruction for execution speculatively. A determination is made whether the instruction executed correctly. The instruction is routed to a replay mechanism if the instruction did not execute correctly. A determination is made whether a replay tornado exists. The instruction is routed for re-execution if the instruction executed incorrectly and no replay tornado exists. Breaking the replay tornado if the replay tornado exists. Replay safe instructions in the pipeline are retired. Non-replay safe instructions in the pipeline are marked for re-execution. The non-replay safe instructions are rescheduled for re-execution.

Abstract: A microcode branch predictor is presented. In an embodiment for a microcode branch predictor the microcode branch predictor includes a first input to accept macrocode instruction address data, a second input to accept microcode instruction address data, a processor to convert the macrocode instruction address data and microcode instruction address data to a value, an index to cross-reference the value to a microcode branch instruction result, and an output to signal whether the microcode branch instruction result is taken or not taken.