Abstract: A dishwasher apparatus includes a dish rack having a wire member, and a feed tube for a spray arm rotatably disposed beneath the dish rack. An intensive washing zone is provided in a region of the dish rack, the intensive washing zone including a rod-shaped pipe element attached to the wire member and having an outlet nozzle. A pipe branch for the intensive washing zone is provided, the pipe branch being disposed in a region of the feed tube and communicating with the pipe element via a T-piece. An actuator is provided that cooperates with the pipe element so as to enable the intensive washing zone to be activated and deactivated.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: An insert for use with a dish washer provided with a rotary spray arm having a nozzle therein and with at least one rinsing basket. The insert is provided at least one receptacle for securely supporting a bottle with its opening in alignment with the rotary path of movement of the nozzle. Protrusions are provided in the receptacle for resiliently maintaining a bottle in its position.

Abstract: A system with a transmitter for transmitting digital data via an interface to a receiver. The interface has at least one data line and a clock line. A clock generator supplies a clock signal to the clock line. The receiver uses the clock signal received from the clock line for deriving timing information for processing received digital data. The clock signal may have an amplitude that is lower than the power supply voltage VDD, typically less than half of the power supply voltage, and less stringent requirements can be applied to the waveform of the clock signal than traditionally applied to data and clock signals. The clock signals are hereby less power consuming and cause significantly less electromagnetic interference.

Abstract: Circuit configuration for signal transmission from a finite state machine that can be operated at a first clock rate to a finite state machine that can be operated at a second clock rate, the signal from the transmitting finite state machine being transferable through an asynchronous storage element and a synchronous storage element connected thereto, to the receiving finite state machine which is designed for transmitting a reset signal to the asynchronous storage element after the signal transmission.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.