Patents by Inventor Stephan Lassig

Stephan Lassig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865472
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Lam Research Corporation
    Inventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin Moore, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
  • Publication number: 20160233102
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Robert CHEBI, Frank LIN, Jaroslaw W. WINNICZEK, Wan-Lin CHEN, Erin MOORE, Lily ZHENG, Stephan LASSIG, Jeff BOGART, Camelia RUSU
  • Patent number: 9330926
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 3, 2016
    Assignee: Lam Research Corporation
    Inventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin McDonnell, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
  • Publication number: 20090184089
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 23, 2009
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Robert CHEBI, Frank LIN, Jaroslaw W. WINNICZEK, Wan-Lin CHEN, Erin MCDONNELL, Lily ZHENG, Stephan LASSIG, Jeff BOGART, Camelia RUSU
  • Patent number: 6875699
    Abstract: A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: April 5, 2005
    Assignees: Lam Research Corporation, Novellus Sytems, Inc.
    Inventors: Stephan Lassig, S. M. Reza Sadjadi, Vinay Pohray, Si Yi Li, Thomas W. Mountsier, Chiu Chi
  • Publication number: 20050009324
    Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
    Type: Application
    Filed: April 16, 2004
    Publication date: January 13, 2005
    Applicant: Lam Research Corporation
    Inventors: SiYi Li, S.M. Sadjadi, David Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
  • Publication number: 20040038540
    Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
    Type: Application
    Filed: October 5, 2001
    Publication date: February 26, 2004
    Applicant: Lam Research Corporation
    Inventors: SiYi Li, S.M. Reza Sadjadi, David R. Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano