Abstract: A plasma etching process for cleaning laterally exposed p-n junctions of semiconductor elements, in particular power diodes after soldering together the semiconductor chip in question and connection elements is proposed, wherein the etching gases employed are fluorine compounds. Since the process according to the present invention does not involve doping dependence and crystal orientation dependence, it produces essentially vertically oriented chip-edges after etching and as a result a lower failure rate compared to the known wet-etching process. Since numerous rinsing processes can also be dispensed with, the plasma etching process is more suitable for mass production.