Abstract: In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.

Abstract: An embodiment includes a method of performing a measurement using a micro-electro-mechanical system (MEMS) device that includes a plurality of MEMS sensors having different resonant frequencies. The method includes applying an excitation signal to a first port of the MEMS device such that each of the plurality of the MEMS sensors is stimulated by the excitation signal. The method further includes measuring a signal at a second port of the MEMS device and determining a measured value based on the measuring the signal.

Abstract: According to an embodiment, a sensor circuit includes a sigma-delta analog to digital converter (ADC), a dithered clock coupled to the sigma-delta ADC, and a supply voltage circuit coupled to the sigma-delta ADC. The sigma-delta ADC is configured to be coupled to a low frequency transducer, and the dithered clock is configured to control of the sigma-delta ADC based on a dithered clock signal.

Abstract: A measurement method includes generating, by a sensor, a response signal in response to an excitation signal. The method also includes generating a sampling clock signal in accordance with a pseudo-random jitter, and sampling the response signal in accordance with the sampling clock signal to determine a plurality of digital samples. The method also includes combining the plurality of digital samples to form a measurement sample.

Abstract: According to an embodiment, a sensor circuit includes a sigma-delta analog to digital converter (ADC), a dithered clock coupled to the sigma-delta ADC, and a supply voltage circuit coupled to the sigma-delta ADC. The sigma-delta ADC is configured to be coupled to a low frequency transducer, and the dithered clock is configured to control of the sigma-delta ADC based on a dithered clock signal.

Abstract: In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.

Abstract: A measurement method includes generating, by a sensor, a response signal in response to an excitation signal. The method also includes generating a sampling clock signal in accordance with a pseudo-random jitter, and sampling the response signal in accordance with the sampling clock signal to determine a plurality of digital samples. The method also includes combining the plurality of digital samples to form a measurement sample.

Abstract: An embodiment includes a method of performing a measurement using a micro-electro-mechanical system (MEMS) device that includes a plurality of MEMS sensors having different resonant frequencies. The method includes applying an excitation signal to a first port of the MEMS device such that each of the plurality of the MEMS sensors is stimulated by the excitation signal. The method further includes measuring a signal at a second port of the MEMS device and determining a measured value based on the measuring the signal.

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract: The invention concerns the adjustment of an oscillation frequency of an oscillator, in particular the digital coarse adjustment of a PLL oscillator by means of a circuit arrangement comprising at least one pair of capacitors (C, C?), of which first terminals are connected with the oscillator, and second terminals can selectively be connected by means of a switching arrangement with a first reference potential (vss), in order to incorporate the capacitor pair (C, C?) into an oscillating circuit of the oscillator, wherein the circuit arrangement comprises: first FETs (T1, T1?) for the respective connection of the second terminals with the first reference potential (vss), a second FET (T2) for the connection of the second terminals with each other, and third FETs (T3, T3?) for the respective connection of the second terminals with a second reference potential (vdd), which differs from the first reference potential (vss).

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127).

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127).