Patents by Inventor Stephan Ollitrault
Stephan Ollitrault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11394383Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.Type: GrantFiled: June 8, 2021Date of Patent: July 19, 2022Assignee: NXP USA, Inc.Inventors: Hongwei Liu, Olivier Tico, Stephan Ollitrault
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Patent number: 11342600Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.Type: GrantFiled: June 8, 2021Date of Patent: May 24, 2022Assignee: NXP USA, Inc.Inventors: Hongwei Liu, Olivier Tico, Stephan Ollitrault
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Publication number: 20220006132Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.Type: ApplicationFiled: June 8, 2021Publication date: January 6, 2022Inventors: Hongwei Liu, Olivier Tico, Stephan Ollitrault
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Publication number: 20220006456Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.Type: ApplicationFiled: June 8, 2021Publication date: January 6, 2022Inventors: Hongwei LIU, Olivier Tico, Stephan Ollitrault
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Patent number: 10649040Abstract: An apparatus for determining the occurrence of a leakage current between a series connected electrochemical battery cells, comprising: a first cell connection terminal for connection to a first cell's first terminal via first filter circuitry; a second cell connection terminal for connection, via second filter circuitry, to a connection between the first cell's second terminal and a second cell's first terminal, the first and second cell adjacent in the series arrangement; a first cell balancing terminal for connection to the first cell's first terminal bypassing the first filter circuitry; a second cell balancing terminal for connection to the connection between the first cell's second terminal and the second cell's first cell terminal; balancing circuitry for providing a connection between the cell balancing terminals; the apparatus configured to provide for identification of a leakage current based at least on a voltage between the cell connection terminals and the cell balancing terminals.Type: GrantFiled: July 25, 2017Date of Patent: May 12, 2020Assignee: NXP USA, Inc.Inventors: Stephan Ollitrault, Savino Luigi Lupo
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Publication number: 20180149689Abstract: An apparatus for determining the occurrence of a leakage current between a series connected electrochemical battery cells, comprising: a first cell connection terminal for connection to a first cell's first terminal via first filter circuitry; a second cell connection terminal for connection, via second filter circuitry, to a connection between the first cell's second terminal and a second cell's first terminal, the first and second cell adjacent in the series arrangement; a first cell balancing terminal for connection to the first cell's first terminal bypassing the first filter circuitry; a second cell balancing terminal for connection to the connection between the first cell's second terminal and the second cell's first cell terminal; balancing circuitry for providing a connection between the cell balancing terminals; the apparatus configured to provide for identification of a leakage current based at least on a voltage between the cell connection terminals and the cell balancing terminals.Type: ApplicationFiled: July 25, 2017Publication date: May 31, 2018Inventors: Stephan OLLITRAULT, Savino Luigi Lupo
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Patent number: 8237424Abstract: A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.Type: GrantFiled: January 18, 2006Date of Patent: August 7, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Arlette Marty-Blavier, Philippe Lance, Stephan Ollitrault, Yean Ling Teo
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Publication number: 20100283444Abstract: A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.Type: ApplicationFiled: January 18, 2006Publication date: November 11, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Arlette Marty-Blavier, Philippe Lance, Stephan Ollitrault, Yean Ling Teo
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Patent number: 6069493Abstract: An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.Type: GrantFiled: November 28, 1997Date of Patent: May 30, 2000Assignee: Motorola, Inc.Inventors: John M. Pigott, Stephan Ollitrault, Damon Peter Broderick