Abstract: A method for reading out a memory cell, and a device to be used for reading out a memory cell. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value, wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.

Abstract: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.

Abstract: Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).

Abstract: A method for reading out a memory cell, and a device to be used for reading out a memory cell is disclosed. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value (Uref), wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.

Abstract: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.

Abstract: The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a first voltage supply node (13) in a latch circuit (11), the voltage supply node (13) being coupled to a control connection on the transistor (10); (b) a reference-ground potential is applied to a second voltage supply node (14) in the latch circuit (11), the second voltage supply node (14) being connected to a source connection on the transistor (10); (c) the latch circuit (11) is set to a predetermined state, which turns the transistor (10) on or off; (d) the potential at the second voltage supply node (14) is lowered; and (e) the potential at the first voltage supply node (13) is lowered if the potential difference between the first and second voltage supply nodes (13, 14) exceeds a predetermined threshold value.

Abstract: Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).

Abstract: The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a first voltage supply node (13) in a latch circuit (11), the voltage supply node (13) being coupled to a control connection on the transistor (10); (b) a reference-ground potential is applied to a second voltage supply node (14) in the latch circuit (11), the second voltage supply node (14) being connected to a source connection on the transistor (10); (c) the latch circuit (11) is set to a predetermined state, which turns the transistor (10) on or off; (d) the potential at the second voltage supply node (14) is lowered; and (e) the potential at the first voltage supply node (13) is lowered if the potential difference between the first and second voltage supply nodes (13, 14) exceeds a predetermined threshold value.