Patents by Inventor Stephan Rotter

Stephan Rotter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6892157
    Abstract: A circuit and method to automatically identify and manipulate a pulse in each of a sequence of clocking signals for an integrated circuit includes a clock manipulation circuit to manipulation the identified pulse including to shrink or otherwise alter the identified pulse; and a pulse identification circuit to automatically and algorithmically identify each pulse to be shrunk.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Darren Slawecki, Stephan Rotter
  • Patent number: 6883127
    Abstract: An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated circuit by a coupled tester, to compare on the die the saved states to the state of the scan latches in a subsequent exercise of the integrated circuit, and to transmit the result of the comparison to the tester, rather to have to transmit to the tester the scan latch states for a comparison analysis after each exercise of the integrated circuit. The apparatus and method include deriving on the die a signature of the saved scan latch states, and comparing on the die the signature of an exercise of the integrated circuit and subsequently exercise of the integrated circuit. The invention also includes generating on the die a scan latch latching clock for consecutively exercising the integrated circuit without determining off the die, and sending to the die, for each iteration, the latching clock.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Darren Slawecki, Stephan Rotter
  • Publication number: 20030005379
    Abstract: An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated circuit by a coupled tester, to compare on the die the saved states to the state of the scan latches in a subsequent exercise of the integrated circuit, and to transmit the result of the comparison to the tester, rather to have to transmit to the tester the scan latch states for a comparison analysis after each exercise of the integrated circuit. The apparatus and method include deriving on the die a signature of the saved scan latch states, and comparing on the die the signature of an exercise of the integrated circuit and subsequently exercise of the integrated circuit. The invention also includes generating on the die a scan latch latching clock for consecutively exercising the integrated circuit without determining off the die, and sending to the die, for each iteration, the latching clock.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 2, 2003
    Inventors: Darren Slawecki, Stephan Rotter
  • Publication number: 20030005366
    Abstract: A circuit and method to automatically identify and manipulate a pulse in each of a sequence of clocking signals for an integrated circuit includes a clock manipulation circuit to manipulation the identified pulse including to shrink or otherwise alter the identified pulse; and a pulse identification circuit to automatically and algorithmically identify each pulse to be shrunk.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 2, 2003
    Inventors: Darren Slawecki, Stephan Rotter