Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.

Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: In accordance with an embodiment, a method of reconstructing a periodic signal includes receiving random electronic samples of the periodic signal from a sensing circuit, sorting, by a processor, the electronic samples in a sequential order to form ordered samples, and estimating, by the processor, a shape of the periodic signal based on the ordered samples

Abstract: In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.

Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: A method to detect tampering of data includes constant acquiring of raw measurement data in a sensor unit. The raw measurement data of a defined time interval is processed in a metrology unit to obtain first measurement results. The first measurement results are transmitted to an authority at defined time instances via a communication channel. A defined fraction of raw measurement data is transmitted to the authority in a random manner via the communication channel. The raw measurement data of the defined time interval is processed at the authority to obtain second measurement results. The first and second measurement results of a time interval are compared.

Abstract: A method to detect tampering includes constant acquiring of measurement raw data in a sensor unit; processing of measurement raw data of a defined time interval in a metrology unit, obtaining first measurement results; at least one of storing of the first measurement results and transmitting of the first measurement results to an authority at defined time instances via a communication channel; at least one of storing of a defined fraction of measurement raw data and transmitting of a defined fraction of measurement raw data to the authority in a random manner via the communication channel; processing of the measurement raw data of the defined time interval at the authority, obtaining second measurement results; and comparing the first and second measurement results of a time interval.

Abstract: An SPI switch allows selection of a BIOS memory transparent to a Southbridge chipset component. The SPI switch provides address translation to a selected BIOS memory area under the control of a security module processor. The SPI switch also provides command filtering to prevent commands that represent a security risk such as bulk erase commands. Because the SPI switch allows transparent redirection between BIOS programs, booting in different operating modes may be supported without any changes to the basic computer architecture or major chipset components.