Abstract: A method for fabricating semiconductor based sensor devices with sensors which are in communication with the environment surrounding the sensor devices, and such a sensor device is described. The method comprises the steps of providing a semiconductor-based device wafer, fabricating a plurality of sensors on the semiconductor-based device wafer, providing a capping wafer, and attaching the capping wafer on the device wafer with each sensor arranged below a recess of the capping wafer. The capping wafer comprises at least one gas permeable section between each recess and the second side, to provide a gas passage between the recess and the environment surrounding the sensor device. The method further comprises the steps of applying a protective layer on all gas permeable sections of the capping wafer, dividing the device wafer and the attached capping wafer into individual sensor devices, and removing the protective layer from all gas permeable sections.

Abstract: A method for fabricating semiconductor-based sensor devices and such a sensor device are described. The sensor devices comprise sensors comprising micro- and/or nanostructures which are in communication with the environment surrounding the sensor devices. The method comprises the steps of providing a semiconductor-based device wafer, fabricating a plurality of sensors on the semiconductor-based device wafer (1), providing (102) a capping wafer, attaching a first side of the capping wafer on the device wafer with each sensor arranged below a recess. The capping wafer comprises, between the recesses, a plurality of holes extending from the second side, wherein the holes are in fluid communication with the cavities by passages arranged between contact areas when the capping wafer has been attached to the device wafer.

Abstract: A control device (2), for a medical apparatus, having at least one sensor (5) for three dimensionally detecting an object (8) which is configured to render graspable a vector (10) for a direction by its alignment is provided, wherein the object (8) is directed to a target area, and the vector (10) generates an intersection point with a surface of the target area. The control device (2) is adapted to recognize in which target area the intersection point is located and to actuate a predefined action for the target area by the medical apparatus.

Abstract: A method for the construction an LED light module, having a printed circuit board, on which at least one LED lamp is accommodated, and having at least one optical element, into which the light generated by the LED lamp can be emitted, wherein the optical element has mounting pins and wherein holes are formed in the printed circuit board, such that the optical element is arranged on the printed circuit board by an insertion of the mounting pins in the holes, wherein the method comprises at least the following steps: arrangement of at least one LED lamp on a mounting surface of the printed circuit board, measurement of the position of the LED lamp in the plane of the mounting surface of the printed circuit board, creation of the holes in the printed circuit board at a position that is dependent on the measured position of the LED lamp in the plane of the mounting surface, and arrangement of the optical element on the printed circuit board by means of an insertion of the mounting pins in the holes.

Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Abstract: An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Abstract: An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored data item being refreshed at the frequency of the frequency signal. The frequency generation unit generates the frequency signal at a first frequency on the basis of a chip temperature detected by the temperature sensor when a first state of the command signal is applied and the frequency generation unit generates the frequency signal at a second frequency, which is changed in comparison with the first frequency, at the same chip temperature when a second state of the command signal is applied.

Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Abstract: An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.

Abstract: An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Abstract: In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip (1) comprises at least one contact (2) to be soldered or is electrically conductively connected to at least one contact (14d) to be soldered that is situated outside the semiconductor chip. The semiconductor chip (1) furthermore comprises a temperature sensor device (3), which determines a measurement quantity corresponding to the temperature. A processing device (4, 5) has an analog-to-digital converter (5), which is electrically conductively connected to the temperature sensor device (3) and converts the measurement quantity into at least one storable signal that represents the temperature loading. A voltage supply device (10), which is electrically conductively connected to the temperature sensor device (3) and the processing device (4, 5), supplies these components with an operating voltage. A data memory (6) serves for storing the at least one storable signal.

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Abstract: An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Abstract: An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened.

Abstract: An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor.

Abstract: A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.

Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Abstract: A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells. The first units of memory cells are tested with regard to their functionality. In the case of a defect ascertained in one of the first units, a number of redundant units is programmed as an associated cluster for replacing one or more of the first units. In this way, a repair element is formed with a cluster size corresponding to the number of redundant units. The cluster size of respective repair elements is set in a variable manner by a redundancy circuit. As a result, in a test and repair operation, a comparatively short test time of the memory is made possible in conjunction with a yield that remains good.

Abstract: An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit.