Abstract: Compounds of formula (I), processes for their production and their use as pharmaceuticals are described herein.

Abstract: A torque-limiting assembly for a surgical powertool has an input shaft and an output shaft. Two relatively rotatable parts of the assembly are configured to be locked against relative rotation by at least one shearable piece for torque transfer between the input shaft and the output shaft up to a torque limit. The assembly further comprises at least one shear off structure rotationally fixed to one of the two relatively rotatable parts for shearing off a portion of the at least one shearable piece above the torque limit so as to unlock the two relatively rotatable parts for relative rotation.

Abstract: A control device (2), for a medical apparatus, having at least one sensor (5) for three dimensionally detecting an object (8) which is configured to render graspable a vector (10) for a direction by its alignment is provided, wherein the object (8) is directed to a target area, and the vector (10) generates an intersection point with a surface of the target area. The control device (2) is adapted to recognize in which target area the intersection point is located and to actuate a predefined action for the target area by the medical apparatus.

Abstract: A method for the construction an LED light module, having a printed circuit board, on which at least one LED lamp is accommodated, and having at least one optical element, into which the light generated by the LED lamp can be emitted, wherein the optical element has mounting pins and wherein holes are formed in the printed circuit board, such that the optical element is arranged on the printed circuit board by an insertion of the mounting pins in the holes, wherein the method comprises at least the following steps: arrangement of at least one LED lamp on a mounting surface of the printed circuit board, measurement of the position of the LED lamp in the plane of the mounting surface of the printed circuit board, creation of the holes in the printed circuit board at a position that is dependent on the measured position of the LED lamp in the plane of the mounting surface, and arrangement of the optical element on the printed circuit board by means of an insertion of the mounting pins in the holes.

Abstract: A torque-limiting assembly for a surgical powertool has an input shaft and an output shaft. Two relatively rotatable parts of the assembly are configured to be locked against relative rotation by at least one shearable piece for torque transfer between the input shaft and the output shaft up to a torque limit. The assembly further comprises at least one shear off structure rotationally fixed to one of the two relatively rotatable parts for shearing off a portion of the at least one shearable piece above the torque limit so as to unlock the two relatively rotatable parts for relative rotation.

Abstract: New polymer concentrates on the basis of polymer additives, like e.g. fillers and flame-retardants, are provided which have in particular an increased bulk density compared to the polymer additives as such. This increased bulk density leads to a substantial improvement in the processability of such concentrates, their dispersibility during compounding and the properties of the resulting polymer compound. Processing improvements include less dust, faster processing and more homogeneous additive dispersion. The invention also provides a process for preparing such new polymer concentrates, a process for preparing polymer compounds containing the new polymer concentrates, the respective polymer compounds and a process for preparing formed parts thereof. Such formed parts have more uniform properties such as density, wall thickness, and in case of the flame-retardants more homogeneous and consistent flame retardancy.

Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: New polymer concentrates on the basis of polymer additives, like e.g. fillers and flame-retardants, are provided which have in particular an increased bulk density compared to the polymer additives as such. This increased bulk density leads to a substantial improvement in the processability of such concentrates, their dispersibility during compounding and the properties of the resulting polymer compound. Processing improvements include less dust, faster processing and more homogeneous additive dispersion. The invention also provides a process for preparing such new polymer concentrates, a process for preparing polymer compounds containing the new polymer concentrates, the respective polymer compounds and a process for preparing formed parts thereof. Such formed parts have more uniform properties such as density, wall thickness, and in case of the flame-retardants more homogeneous and consistent flame retardancy.

Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Abstract: A device can be used for refreshing memory contents of first and second memory cells. The memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time. A pre-charge circuit is provided for bit lines for the first memory cells and the second memory cells. A controller may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.

Abstract: In a method of making wine comprising fermenting a mixture in a main batch container to produce wine and transferring the wine from the main batch container to a plurality of bottles, at least a portion of the wine is exposed to a vacuum pressure during the wine making process prior to bottling. The wine is thus degassed without the stress of agitation or filtering being required. The wine is also transferable either for racking to remove sediment or when bottling in a manner which reduces sediment uptake into the siphon tubes and which reduces stress from agitations applied to the wine using vacuum pressure.

Abstract: A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.

Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Abstract: An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Abstract: A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the memory device or an internally generated voltage of the memory device lies below a predetermined threshold value.

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: A device is disclosed for refreshing memory contents of first and second memory cells, wherein the memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time, having a pre-charge circuit for bit lines for the first memory cells and the second memory cells, and having a controller which may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.

Abstract: A memory circuit comprises a memory cell array with dynamic memory cells arranged on word lines and bit lines, a selection unit providing selection information and a refresh circuit selecting the memory cells in each case in dependence on the selection information and refreshing the selected memory cells so that any information stored therein is retained in each case.

Abstract: Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.