Patents by Inventor Stephan Waidmann

Stephan Waidmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8922453
    Abstract: Antenna systems, such as an active antenna system (AAS), can include active and passive electronic components located closely together inside an antenna system. Such systems may benefit from variable adaptation of active antenna system radio frequency signal filtering. An apparatus can include an active part on a first end of a signal path within a sealed enclosure. The apparatus can also include a radiator part on a second end of the signal path within the sealed enclosure. The apparatus can further include an intermediate part, which includes at least one of an additional filter part or a customized passive part, positioned between the active part and the radiator part along the signal path between the first signal side and the second signal side.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: December 30, 2014
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Stephan Waidmann, Elmar Guha
  • Publication number: 20140028529
    Abstract: Antenna systems, such as an active antenna system (AAS), can include active and passive electronic components located closely together inside an antenna system. Such systems may benefit from variable adaptation of active antenna system radio frequency signal filtering. An apparatus can include an active part on a first end of a signal path within a sealed enclosure. The apparatus can also include a radiator part on a second end of the signal path within the sealed enclosure. The apparatus can further include an intermediate part, which includes at least one of an additional filter part or a customized passive part, positioned between the active part and the radiator part along the signal path between the first signal side and the second signal side.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: NOKIA SIEMENS NETWORKS OY
    Inventors: Stephan Waidmann, Elmar Guha
  • Patent number: 8445964
    Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: May 21, 2013
    Assignee: GlobalFoundries Inc.
    Inventors: Rohit Pal, Stephan Waidmann
  • Publication number: 20130049124
    Abstract: An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Stephan Waidmann, Stefan Flachowsky, Peter Baars, Rainer Giedigkeit
  • Publication number: 20120112281
    Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 10, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Rohit PAL, Stephan Waidmann
  • Patent number: 8119464
    Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: February 21, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Stephan Waidmann
  • Publication number: 20110266638
    Abstract: A metal silicide in sophisticated semiconductor devices may be provided in a late manufacturing stage on the basis of contact openings, wherein the deposition of the contact material, such as tungsten, may be efficiently combined with the silicidation process. In this case, the thermally activated deposition process may initiate the formation of a metal silicide in highly doped semiconductor regions.
    Type: Application
    Filed: December 9, 2010
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Rainer Giedigkeit, Robert Binder, Stephan Waidmann
  • Publication number: 20110062519
    Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Stephan Waidmann