Abstract: A steering gear for an electromechanical steering system for a vehicle includes an input shaft that can be coupled or connected to a steering column of the steering system, a segment shaft that can be coupled or connected to a steering column lever of the steering system, an angular gear, a servo gear, and an electric motor for driving the servo gear. The angular gear is designed as a bevel gear. The input shaft and the electric motor are connected to the servo gear. The servo gear is connected to the angular gear. The angular gear is connected to the segment shaft. The angular gear is formed to transmit torque from the servo gear to the segment shaft via two transmission paths.

Abstract: Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n?-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.

Abstract: A silicon carbide power device having a low on-resistance Ron and a method for manufacturing the same are provided. The silicon carbide power device comprises a first conductivity-type substrate, a plurality of silicon carbide layer stacks, a continuous insulating layer and a gate electrode layer. Each silicon carbide layer stack comprises the following layers stacked on the substrate: a first conductivity-type drain layer, a second conductivity-type channel layer and a first conductivity-type source layer. A plurality of first insulating layer portions laterally cover and surround at least the drain layer and the channel layer of each silicon carbide layer stack. Each point of each channel layer is laterally sandwiched between two opposing portions of the gate electrode layer, wherein the two opposing portions have a distance (d) of less than 2 ?m along a straight line extending through that point of that channel layer.

Abstract: Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.

Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).

Abstract: In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).

Abstract: An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 1018 atoms/cm?3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Abstract: A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

Abstract: A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, an n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Abstract: Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n?-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.

Abstract: A method for depositing a monocrystalline semiconductor layer consisting of a first element and a second element, wherein the first elements is fed as part of a hydride, and the second element is fed as part of a halide, together with a carrier gas, into a process chamber of a reactor, wherein radicals are produced from the hydride at a distance away from a surface of a semiconductor substrate, wherein at a temperature below a decomposition temperature of the radicals, at a total pressure of the gas in the process chamber sufficiently low to avoid a reverse reaction of the radicals in the gas phase the radicals and the halide are brought to the surface of the semiconductor substrate which is heated to a substrate temperature lower than the decomposition temperature, wherein heat released during a first exothermic chemical reaction drives a second endothermic chemical reaction.

Abstract: A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm?2, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as Ge2H6 or Si2H6; providing a halide of a second IV element (B), such as SnCl4; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A method for autonomous map generation by a robot comprising: instructing the robot to traverse a route within an environment in which the robot is deployed; while following the route, causing the robot to collect sensor data to identify features in the environment and to generate an initial map of areas in environment that have been traversed; upon completion of the route, autonomously generating a map of valid areas of the environment by moving throughout the environment while collecting sensor data; while autonomously generating the map, determining that a particular area is potentially invalid by detecting features that are previously unknown to the robot; generating and providing an electronic message to an operator of the robot comprising sensor data of the particular area and a prompt requesting information indicating whether the particular area is valid or invalid; upon receiving a response from the operator, continuing autonomously generating the map according to the response wherein if the particula

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A method for autonomous sensor data collection by a robot comprising: receiving, at the robot, a digitally stored initial map representing a plurality of locations within an environment, wherein each location of the plurality of locations is associated with first sensor data; determining, based on the initial map and one or more stored parameters, whether one or more portions of the initial map should be updated; in response to determining one or more portions of the initial map should be updated, the robot calculating a route to one or more target locations corresponding to the one or more portions of the initial map, and the robot physically traversing the environment on the route; during traversal of the route, collecting second sensor data from one or more sensors of the robot at each target location of the one or more target locations; generating updated map data associating each target location of the one or more locations with respective updated sensor data based on the second sensor data.

Abstract: A method for autonomous sensor data collection by a robot comprising: receiving, at the robot, a digitally stored initial map representing a plurality of locations within an environment, wherein each location of the plurality of locations is associated with first sensor data; determining, based on the initial map and one or more stored parameters, whether one or more portions of the initial map should be updated; in response to determining one or more portions of the initial map should be updated, the robot calculating a route to one or more target locations corresponding to the one or more portions of the initial map, and the robot physically traversing the environment on the route; during traversal of the route, collecting second sensor data from one or more sensors of the robot at each target location of the one or more target locations; generating updated map data associating each target location of the one or more locations with respective updated sensor data based on the second sensor data.

Abstract: A method for autonomous map generation by a robot comprising: instructing the robot to traverse a route within an environment in which the robot is deployed; while following the route, causing the robot to collect sensor data to identify features in the environment and to generate an initial map of areas in environment that have been traversed; upon completion of the route, autonomously generating a map of valid areas of the environment by moving throughout the environment while collecting sensor data; while autonomously generating the map, determining that a particular area is potentially invalid by detecting features that are previously unknown to the robot; generating and providing an electronic message to an operator of the robot comprising sensor data of the particular area and a prompt requesting information indicating whether the particular area is valid or invalid; upon receiving a response from the operator, continuing autonomously generating the map according to the response wherein if the particula