Abstract: Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.

Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).

Abstract: A superjunction power semiconductor device comprising a substrate, a plurality of core structures and a plurality of annular shell structures. Each core structure has a cylindrical shape extending in a direction perpendicular to a main surface of the substrate and comprising a first semiconductor material of a first conductivity type. Each shell structure surrounds one of the core structures on its outside and comprises a second semiconductor material of a second conductivity type.

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p?/n?/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n?/p?/n+ structures.

Abstract: A manufacturing method for a power semiconductor device, comprising forming at least one insulating layer on a surface of a crystalline growth substrate, the at least one insulating layer comprising at least one cavity extending in a lateral direction within the at least one insulating layer; selectively growing a wide bandgap, WBG, semiconductor material within the cavity to form a lateral epi-layer, wherein a surface area of the growth substrate exposed through at least one passage formed between the at least one cavity and the growth substrate is uses as a seed area for epitaxially growing the WBG semiconductor material; and forming at least one semiconductor junction, in particular a pn junction, a np junction or a Schottky junction, within or at an end of the selectively grown WBG semiconductor material.

Abstract: A method comprises providing a semiconductor body with a top side. A mask is applied on the top side of the semiconductor body, wherein the mask comprises at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. A channel region of a first conductivity type is formed in the semiconductor body in the area of the at least one first section. Forming the channel region comprises implanting first-type dopants through the top side into the semiconductor body. An auxiliary layer is deposited on a lateral side of the at least one second section, the lateral side facing towards the at least one first section.

Abstract: A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.

Abstract: An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 1018 atoms/cm?3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Abstract: A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p?/n?/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n?/p?/n+ structures.

Abstract: A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

Abstract: A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Abstract: The present disclosure relates to a method for forming an ohmic contact on a wide-bandgap semiconductor device comprising: shallow implanting a dopant through a first surface of a wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region of a wide-bandgap semiconductor material, thermal treatment of the interface region comprising the implanted dopant at a temperature below 1100° C., and depositing a metal material on top of the at least one interface region to form at least one ohmic contact region. The present disclosure further relates to a wide-bandgap semiconductor device comprising a semiconductor body or epitaxial layer comprising a wide-bandgap semiconductor material, at least one interface region which is doped and arranged within the wide-bandgap semiconductor material, and at least one ohmic contact region arranged on top of the at least one interface region.

Abstract: Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n?-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.

Abstract: A silicon carbide power device having a low on-resistance Ron and a method for manufacturing the same are provided. The silicon carbide power device comprises a first conductivity-type substrate, a plurality of silicon carbide layer stacks, a continuous insulating layer and a gate electrode layer. Each silicon carbide layer stack comprises the following layers stacked on the substrate: a first conductivity-type drain layer, a second conductivity-type channel layer and a first conductivity-type source layer. A plurality of first insulating layer portions laterally cover and surround at least the drain layer and the channel layer of each silicon carbide layer stack. Each point of each channel layer is laterally sandwiched between two opposing portions of the gate electrode layer, wherein the two opposing portions have a distance (d) of less than 2 ?m along a straight line extending through that point of that channel layer.

Abstract: Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.

Abstract: In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).

Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).

Abstract: An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 1018 atoms/cm?3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Abstract: A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.