Patents by Inventor Stephane Allegret-Maret
Stephane Allegret-Maret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220181390Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.Type: ApplicationFiled: December 6, 2021Publication date: June 9, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Thierry BERGER, Stephane ALLEGRET-MARET
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Patent number: 10199413Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.Type: GrantFiled: December 12, 2017Date of Patent: February 5, 2019Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS(CROLLES 2) SASInventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
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Patent number: 10170475Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.Type: GrantFiled: March 3, 2017Date of Patent: January 1, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Stephane Allegret-Maret, Kangguo Cheng, Bruce Doris, Prasanna Khare, Qing Liu, Nicolas Loubet
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Patent number: 10038075Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.Type: GrantFiled: February 21, 2017Date of Patent: July 31, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Stephane Allegret-Maret, Kangguo Cheng, Bruce Doris, Prasanna Khare, Qing Liu, Nicolas Loubet
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Publication number: 20180102387Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.Type: ApplicationFiled: December 12, 2017Publication date: April 12, 2018Inventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
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Patent number: 9859319Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.Type: GrantFiled: October 27, 2015Date of Patent: January 2, 2018Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
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Publication number: 20170179137Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: STEPHANE ALLEGRET-MARET, KANGGUO CHENG, BRUCE DORIS, PRASANNA KHARE, QING LIU, NICOLAS LOUBET
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Patent number: 9685475Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.Type: GrantFiled: September 8, 2015Date of Patent: June 20, 2017Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
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Publication number: 20170170299Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.Type: ApplicationFiled: February 21, 2017Publication date: June 15, 2017Inventors: STEPHANE ALLEGRET-MARET, KANGGUO CHENG, BRUCE DORIS, PRASANNA KHARE, QING LIU, NICOLAS LOUBET
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Patent number: 9620507Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.Type: GrantFiled: May 31, 2013Date of Patent: April 11, 2017Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
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Patent number: 9620506Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.Type: GrantFiled: May 31, 2013Date of Patent: April 11, 2017Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
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Publication number: 20160233258Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.Type: ApplicationFiled: October 27, 2015Publication date: August 11, 2016Inventors: Axel CROCHERIE, Jean-Pierre ODDOU, Stéphane ALLEGRET-MARET, Hugues LEININGER
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Publication number: 20160099278Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.Type: ApplicationFiled: September 8, 2015Publication date: April 7, 2016Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
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Patent number: 9224775Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.Type: GrantFiled: July 30, 2014Date of Patent: December 29, 2015Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Jean-Pierre Carrere, Patrick Gros D'Aillon, Stephane Allegret-Maret, Jean-Pierre Oddou
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Patent number: 9006816Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.Type: GrantFiled: March 28, 2013Date of Patent: April 14, 2015Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
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Publication number: 20150035106Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.Type: ApplicationFiled: July 30, 2014Publication date: February 5, 2015Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Jean-Pierre Carrere, Patrick Gros D'Aillon, Stephane Allegret-Maret, Jean-Pierre Oddou
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Publication number: 20140353718Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Applicants: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
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Publication number: 20140353717Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Applicants: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
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Patent number: 8860123Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.Type: GrantFiled: March 28, 2013Date of Patent: October 14, 2014Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
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Publication number: 20140291750Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Prasanna KHARE, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris