Abstract: Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.

Abstract: An integrated circuit includes a processor and a program memory device on a common substrate. The memory device is able to deliver to the processor VLIW instructions with at least m operative fields. The memory device comprises: a dictionary memory comprising dictionary instructions each having at least m dictionary elementary instructions; an instructions memory having primary instructions each associated with a VLIW instruction and containing its data, the address of a dictionary instruction, and m masking bits; and m selection devices respectively controlled by the masking bits and each delivering either an NOP instruction, or the dictionary elementary instruction corresponding to the masking bit, so as to reconstruct, by combination with the data of the primary instruction, the VLIW instruction.

Abstract: Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.

Abstract: An electronic device for data processing may include p synchronous processor cores each respectively clocked by one of p clock signals all having a same period T and being phase-shifted by 2 &pgr;/p relative to one other. The electronic device may further include a single access shared memory with an access time less than or equal to T/p. The memory may be clocked by an access signal with a period T/p and that is synchronous with the clock signals. The processors cores may sequentially and cyclically access the memory at consecutive intervals spaced apart in time with a period equal to T/p. The electronic device is particularly well suited for use in audio processors of digital versatile disk (DVD) decoders, for example.