Abstract: A method of transcoding digital data which, at the start, appear in the form of a thermometric code, the successive values of which may be represented by a first bit matrix (columns 1 to 8). The method uses an intermediate code defined by a second matrix (low significance), (columns (1), (2), (3) and (4)), and by a third matrix (high significance), (columns 4 and 8), which is extracted from the first matrix. The intermediate code delivers digital words which are shorter than the starting words and permits a later transformation into a binary code (columns [1], [2], [3], [4],) which is very simple. A decoder and a converter using this method is described where the decoder is organized so as to first produce the values of the intermediate code and then, the corresponding values in binary code. The converter employs analog gates with multiple inputs instead of the purely logic input blocks of the decoder.

Abstract: The invention relates to a memory having a line decoder provided with a Darlington-type switching stage. When the deselection time T.sub.1 of a line is notably shorter than the intrinsic switching time T.sub.3 of a memory cell (M11 . . . Mnp), a discharge current I.sub.D is temporarily applied to the lower line conductor (1' . . . n') of the line (L1 . . . Ln) which is deselected. To achieve this, the current source I.sub.D is connected to said lower line conductors (1' . . . n') via delay circuits (RL1, DL1 . . . RLn, DLn) having a time constant T.sub.2 which is smaller than T.sub.3 and at least equal to T.sub.1.

Abstract: A differential amplifier stage including a main pair of transistors (T1, T2) having their bases connected to a pair of input terminals (V1, V2) and their collectors coupled to a supply terminal (Vcc) via respective cascode connected transistors (T5, T6). The emitters are interconnected to a current source. An auxiliary pair of transistors (T3T4), have their bases connected to the pair of input terminals, their collectors coupled to a supply voltage (VCC'), and their emitters interconnected to a current source. A summation device supplies a part of the collector current from the auxiliary pair of transistors to the main pair of transistors. The summation device includes a first (R3, R5) and a second (R4, R6) resistor bridge coupled between the collectors of the main pair of transistors and the supply voltage (Vcc') with respective taps on the first and the second resistor bridge coupled to respective collectors for the auxiliary pair of transistors.

Abstract: A power-amplifier cell which comprises an inverting input amplifier made up of a first transistor (T.sub.1) having a collector connected to a first supply-voltage terminal via a first resistor (R.sub.11), and an output stage comprising a second (T.sub.4) and a third (T.sub.6) transistor whose collector-emitter paths are arranged in series. The common point between the second and third transistors forms an output (5) of the power amplifier. The second transistor (T.sub.4) has its base connected to the collector of the first transistor (T.sub.1) and a control signal is applied to the base of the third transistor (T.sub.6) via a second resistor (R.sub.16). Furthermore, a first capacitor (C.sub.1) is arranged in parallel with the first resistor (R.sub.11) and the control signal is the input signal (E) or a fraction thereof. The power amplifier may comprise two cells whose first transistors (T.sub.1) have their emitters coupled to one another.

Abstract: The invention relates to a circuit intended to supply a reference voltage comprising a voltage generator (REF) provided with a supply terminal and an output for supplying a voltage having a given nominal value (V.sub.R) and comprising a differential amplifier (A), fed by a first supply voltage, whose non-inverting input is connected to the output of the voltage generator (REF). An output of the differential amplifier (A) is connected to an input of a follower stage (T) through a controlled switching device (1), the follower stage (T) having its input connected to the first supply voltage through a first resistor (R.sub.1) and having its output, which supplies the said reference voltage (V.sub.D), connected on the one hand to the inverting input of the differential amplifier (A) through a divider bridge and on the other hand to the supply termianl of the voltage generator (REF).

Abstract: A delay circuit with adjustable delay employs a switching flip-flop which includes a differential amplifier (A) having two outputs each one feedback-looped respectively onto two inputs, so as to produce the said switching. The looping is produced by a first (AD1) and a second (AD2) adder, each having a first, a second and a third input. The first inputs are connected to corresponding outputs of the differential amplifier to produce the feedback looping. The second inputs are intended to be connected respectively to a first and a second terminal delivering a signal to be delayed (V.sub.1.sup.+, V.sub.1.sup.-) and the third inputs receive respectively a first and a second control voltage (V.sub.3.sup.+, V.sub.3.sup.-). The delay is a function of the difference between the first and the second control voltage. The outputs of the adders are connected respectively to corresponding inputs of the differential amplifier.

Abstract: An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T.sub.6) has its base connected to the collector of the first transistor (T.sub.3). A first resistor (R.sub.10), a second resistor (R.sub.11) and a third resistor (R.sub.12) are disposed in series between the emitter of the third transistor and a reference voltage (U.sub.REF) source. The point B common to the resistors R.sub.11 and R.sub.12 is coupled to the base of the second transistor (T.sub.4).

Abstract: An integrated circuit comprising a current generator which is switchable to at least two modes. A first stage comprises a current mirror (T.sub.3, T.sub.4) having two branches. A differential pair second stage (T.sub.1, T.sub.2) is either in a balanced state (current output zero) or in an unbalanced state (current source R.sub.10, T.sub.10 supplying a current I.sub.1). In the balanced state a second current source (R.sub.20, T.sub.20) supplies a current which maintains the currents in the two branches of the current mirror constant.