Abstract: A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design.

Abstract: A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design.

Abstract: A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

Abstract: A programmable logic device includes a gate array formed from programmable logic elements, and at least one address decoder structure. The address decoder has a first stage, for receiving bits of an address, and for masking out a first group of least significant bits of said address; a second stage, for comparing a second group of most significant bits of said address with respective comparison bits; and a third stage, for providing an output when all of the bits in said second group of bits of said address match their respective comparison bits. Thus, the address decoder can determine when a received address falls within a range of addresses associated with the address decoder. Multiple address decoders may be provided at spaced apart locations within the gate array, and one address decoder can be associated with each slave device implemented in the gate array. The programmable logic device may be used to implement a bus structure, with a bus master which may be in the form of an embedded processor.

Abstract: A circuit for translating a configuration file used to configure a programmable logic device includes a first register to serially receive configuration data. A second register receives, in parallel, configuration data from the first register. A translation address memory translates an original address for a selected configuration bit of the configuration data to a translated address. A translation memory stores the selected configuration bit at the translated address. Control logic selectively downloads configuration data from the translation memory to a programmable logic device core.