Abstract: The field of the invention is that of the design and use of electronic systems subjected to an ionizing radiation environment of natural or artificial origin. The invention relates to a method for simulating the failure rate of electronic equipment subjected to atmospheric neutron radiation of natural origin. From parameters giving the geographic location of the equipment, which are longitude, latitude and altitude, and from a knowledge of the grid width of the transistors constituting the electronic components of the equipment, this width being representative of the technology employed, the method makes it possible to determine the anticipated failure rate of the equipment due to neutron irradiation.

Abstract: The invention concerns ordering of segments of lines in a network.Since line segments may interact with each other, a principal rank is assigned to each segment, with principal ranks being incremented such that segments interacting with each other have principal ranks in which the difference is at most equal to one unit and all segments on the same line have the same rank.

Abstract: A preferred embodiment comprises, on one face, an encapsulated hybrid circuit that groups together circuits with high density of integration, formed by one or more semiconductor chips, said circuits being mounted on a thin-layer substrate. The thin-layer substrate is grown on one face of a supporting, thick-layer substrate, preferably made of co-baked ceramic. Encapsulate, microelectronic components such as monolithic, integrated circuits are borne on the other face of the substrate. The interconnections among various components and with the exterior are made within and through the layers of the supporting substrate so that no wire or connection appears on the uncovered parts of the substrate. A detachable, elastomer connection scheme enables the connection of the input/output interconnection terminals of the module with the exterior.

Abstract: The support device permits the use of only one type of plate for selecting the different types of integrated circuits having spacing values of 0.3 inch or 0.4 inch or 0.6 inch between the two rows of terminal pins. The plate consists of a parent card in the form of a double-face printed circuit and of a plurality of daughter cards in the form of a multilayer circuit. The integrated circuits are supported by tulip-type plug sockets disposed at intervals in a number of rows in order to conform to the different spacing values. Each dynamic signal is distributed to the integrated-circuit terminal pins having the same reference number via a protection circuit comprising a diode in series, a voltage-dividing bridge and a diode connected in shunt between the common point and ground. Provision is made for U-link matching means in order to apply instead of the dynamic signal a direct-current supply or a ground when so required by the type of integrated circuit to be selected.

Abstract: The selecting system makes use of a bank of amplifiers for successively and sequentially exciting P different types of integrated circuits assembled together in groups. The amplifying channels are periodically enabled one after the other by means of a demultiplexing circuit controlled from a processing and programming unit designated as PPU. The direct-current supplies comprise a programmable supply which is also addressed by the PPU and the output of which is applied to a switching matrix, the matrix being also addressed by the PPU and connected via P outputs respectively to the P groups of integrated circuits. Transmission of the excitation signals to the group of integrated circuits relating to said signals is performed by means of a second switching matrix addressed by the PPU. A mass memory unit such as a microprocessor is associated with the PPU and can have an electric functional test program for programming the excitation signals desired for selection.