Patents by Inventor Stephane Dallaire
Stephane Dallaire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11876649Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: GrantFiled: January 20, 2022Date of Patent: January 16, 2024Assignee: Marvell Asia Pte LtdInventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
-
Patent number: 11855598Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.Type: GrantFiled: August 25, 2022Date of Patent: December 26, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Praveen Prabha, Karthik Raviprakash, Luke Wang, Stephane Dallaire
-
Publication number: 20230402987Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.Type: ApplicationFiled: August 22, 2023Publication date: December 14, 2023Inventors: Stephane DALLAIRE, Ray Luan NGUYEN, Geaffrey HATCHER
-
Patent number: 11750166Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.Type: GrantFiled: January 13, 2021Date of Patent: September 5, 2023Assignee: Marvell Asia Pte. Ltd.Inventors: Stephane Dallaire, Ray Luan Nguyen, Geoffrey Hatcher
-
Publication number: 20230037860Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: ApplicationFiled: January 20, 2022Publication date: February 9, 2023Inventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
-
Publication number: 20220407484Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.Type: ApplicationFiled: August 25, 2022Publication date: December 22, 2022Inventors: Praveen PRABHA, Karthik Raviprakash, Luke Wang, Stephane Dallaire
-
Patent number: 11463059Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.Type: GrantFiled: March 23, 2021Date of Patent: October 4, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Praveen Prabha, Karthik Raviprakash, Luke Wang, Stephane Dallaire
-
Publication number: 20220311403Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Praveen PRABHA, Karthik RAVIPRAKASH, Luke WANG, Stephane DALLAIRE
-
Publication number: 20220224302Abstract: An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.Type: ApplicationFiled: January 13, 2021Publication date: July 14, 2022Inventors: Stephane DALLAIRE, Ray Luan NGUYEN, Geoffrey HATCHER
-
Patent number: 10312873Abstract: Split cascode circuits include multiple cascode paths coupled between voltage supply rails. Each cascode path includes a pair of controllable switches. A feedback path is provided for at least one of the cascode circuit paths. An active load circuit may also have a split cascode structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascode circuits.Type: GrantFiled: January 5, 2018Date of Patent: June 4, 2019Assignee: INPHI CORPORATIONInventors: Florin Pera, Stephane Dallaire, Brian Wall
-
Patent number: 10122472Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.Type: GrantFiled: June 28, 2016Date of Patent: November 6, 2018Assignee: INPHI CORPORATIONInventors: Kevin Parker, Lawrence Tse, Kenji Suzuki, Brian Wall, Stephane Dallaire, Florin Pera
-
Publication number: 20180145650Abstract: Split cascode circuits include multiple cascode paths coupled between voltage supply rails. Each cascode path includes a pair of controllable switches. A feedback path is provided for at least one of the cascode circuit paths. An active load circuit may also have a split cascode structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascode circuits.Type: ApplicationFiled: January 5, 2018Publication date: May 24, 2018Inventors: Florin PERA, Stephane DALLAIRE, Brian WALL
-
Patent number: 9899973Abstract: Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.Type: GrantFiled: March 18, 2016Date of Patent: February 20, 2018Assignee: INPHI CORPORATIONInventors: Florin Pera, Stephane Dallaire, Brian Wall
-
Publication number: 20170373761Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventors: Kevin Parker, Lawrence Tse, Kenji Suzuki, Brian Wall, Stephane Dallaire, Florin Pera
-
Publication number: 20170272046Abstract: Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Applicant: INPHI CORPORATIONInventors: FLORIN PERA, STEPHANE DALLAIRE, BRIAN WALL
-
Patent number: 9742594Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.Type: GrantFiled: December 7, 2016Date of Patent: August 22, 2017Assignee: INPHI CORPORATIONInventors: Stephane Dallaire, Benjamin Smith
-
Patent number: 9660841Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.Type: GrantFiled: September 9, 2016Date of Patent: May 23, 2017Assignee: INPHI CORPORATIONInventors: Stephane Dallaire, Benjamin P. Smith, Travis William Lovitt, Arash Farhoodfar
-
Publication number: 20170118046Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.Type: ApplicationFiled: December 7, 2016Publication date: April 27, 2017Applicant: INPHI CORPORATIONInventors: STEPHANE DALLAIRE, BENJAMIN SMITH
-
Patent number: 9559877Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.Type: GrantFiled: October 23, 2015Date of Patent: January 31, 2017Assignee: INPHI CORPORATIONInventors: Stephane Dallaire, Benjamin Smith
-
Publication number: 20160380784Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.Type: ApplicationFiled: September 9, 2016Publication date: December 29, 2016Inventors: Stephane DALLAIRE, Benjamin P. SMITH, Travis William LOVITT, Arash FARHOODFAR