Patents by Inventor Stephane Dufrenne

Stephane Dufrenne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication of local interconnect lines
    Patent number: 7208363
    Abstract: A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: April 24, 2007
    Assignee: Systems on Silicon Manufacturing Co. Pte. Ltd.
    Inventors: Stephane Dufrenne, Mohd Faizal Zainal Abidin
  • System and method for optical proximity correction
    Publication number: 20060277519
    Abstract: A method of optical proximity correction is described. The method includes selecting all islands, increasing the size of each said island. The facing sides of each island is pulled back equally if island to island spacing is insufficient between two islands. A further step of pulling back equally the facing sides of an island and a continent if island to continent spacing is insufficient between the island and the continent.
    Type: Application
    Filed: June 6, 2005
    Publication date: December 7, 2006
    Inventors: Stephane Dufrenne, Ming Adrian Soh
  • Fabrication of local interconnect lines
    Publication number: 20060252195
    Abstract: A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 9, 2006
    Inventors: Stephane Dufrenne, Mohd Faizal Abidin