Abstract: A switched capacitor array circuit for use in a voltage regulator, including L, M and N banks of capacitor positions disposed intermediate an input node and a ground node, between the input and output nodes and between the output node and the ground node, respectively. Switching circuitry operates to switch three capacitors between a common phase configuration and a gain phase configuration. Two of the capacitors are disposed in one of the L, M and N banks of capacitor positions, with the third capacitor being disposed in a different one of the L, M and N banks of capacitor positions in the common phase configuration. When switched from the common phase to the gain phase configuration, at least one of the three capacitors is moved to a different capacitor position.

Abstract: A band gap circuit that may be implemented in a standard CMOS process including a pair of parasitic vertical PNP transistors operating at a different current density. The PNP transistors have common collectors and common bases and produce a difference in base-emitter voltages which is developed across a resistor so as to produce a current having a positive temperature coefficient. The current is used to produce a positive temperature coefficient voltage which is combined with another voltage having a negative temperature coefficient to produce a band gap reference voltage. A bias voltage is applied between the base and collector of each of the PNP transistors, typically on the order of 500 millivolts. This causes the emitters of the PNP transistors to be at a voltage which can be sensed by an error amplifier implemented with standard N type MOS input transistors while maintaining a capability of operating using a relatively low power supply voltage.

Abstract: A switched capacitor array circuit and method, with the array circuit being coupled between an input node and an output node and which is capable of providing multiple gain states. The array circuit includes an L band of capacitor positions disposed between the input node and a third node, typically the circuit common, an M bank of capacitor positions coupled between the input and output nodes and an N bank of capacitor positions coupled between the output node and the third node. Each of the L, M and N banks of capacitor positions includes series and parallel capacitor positions. In one embodiment, the array includes first, second and third capacitors together with switching circuitry and control circuitry. The control circuitry causes the switching circuitry to switch the array circuit between a common phase configuration and a gain phase configuration so as to provide a gain state value Gsc.