Abstract: M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0?n ?N?1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift T? is calculated by ? i = 0 M - 1 ? ? Idx ? ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.

Abstract: A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.

Abstract: An apparatus and method for the analysis of a periodic signal. One embodiment provides signal values. Signs are assigned to the signal values. The signed signal values are summed to a first sum. At least one signal property is determined on the basis of the first sum.

Abstract: M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0?n ?N?1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift T? is calculated by ? i = 0 M - 1 ? ? ? Idx ? ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.

Abstract: A test apparatus for testing digitized test responses has a generator (2) and a signal extractor (3). The generator (2) uses direct digital synthesis to generate a set of n digital reference signals (xk, yk) which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor (3) contains a test input and a plurality of reference inputs. The test input receives a digitized test response (E) and the reference inputs are connected to the reference signals (xk, yk) which are generated by the generator (2). The signal extractor (3) generates scalar products from a respective reference signal (xk, yk) and the test response (E) and uses said products to calculate whether a combination of reference signals (xk, yk) is contained in the test response (E).

Abstract: System for testing a group of functionally independent memories (102) and for replacing failing memory words of the group of functionally independent memories (102) by redundant memory words, comprising: redundancy means 108) including at least one array of redundant memory words (108a) and address registers (108b) connected to at least one array of redundant memory words (108a); a test means (114); a group of first multiplexers (110) following the test means (114) and preceding the memories (102) and the at least one array of redundant memory words (108a); and a group of second multiplexers (112) following the memories (102) and the at least one array of redundant memory words (108a), wherein each second multiplexer (112) is connectable to the test means (114).

Abstract: System for testing a group of functionally independent memories and for replacing failing memory words

Abstract: Defective pixels of an image sensor are corrected by the device having an interpolator, a defect column memory, and a switch that changing the output signal under the control of the defect column memory. Depending on a defect signal from the defect column memory, input pixel data are output as output pixel data in a defect-free case and pixel data interpolated from adjacent pixel data are output as output pixel data in a defect case. The defect signal is generated from an image line address and an image column address such that a pointer memory is addressed by the image line address, wherein the pointer memory contains a pointer for each of at least some of the image lines, the pointer addressing a defect column memory with column numbers stored therein of defective image columns. The column number is read from the defect column memory, the column number is compared with the column address, and the defect signal is formed from the comparison.