Patents by Inventor Stephane Lacouture

Stephane Lacouture has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for correcting at least one bit error within a coded bit sequence
    Patent number: 10200065
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stephane Lacouture
  • Programming of antifuse cells
    Patent number: 9536622
    Abstract: For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 3, 2017
    Assignee: STMICROELECTRONICS SA
    Inventors: Stephane Lacouture, Joel Damiens
  • PROGRAMMING OF ANTIFUSE CELLS
    Publication number: 20160078963
    Abstract: For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 17, 2016
    Applicant: STMICROELECTRONICS SA
    Inventors: Stephane Lacouture, Joel Damiens
  • APPARATUS AND METHOD FOR CORRECTING AT LEAST ONE BIT ERROR WITHIN A CODED BIT SEQUENCE
    Publication number: 20130346834
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stephane Lacouture
  • Apparatus and method for correcting at least one bit error within a coded bit sequence
    Patent number: 8539321
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stéphane Lacouture
  • Apparatus and Method for Correcting at least one Bit Error within a Coded Bit Sequence
    Publication number: 20120117448
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stéphane Lacouture