Patents by Inventor Stephane Le Provost

Stephane Le Provost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190079284
    Abstract: Techniques and examples pertaining to variable pixel density across a display and control thereof are described. A display controller circuit can receive data from a data source, and control a display device to display the data on a single display panel of the display device. The display panel has a variable pixel density across the display panel.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventor: Stephane Le Provost
  • Patent number: 9411390
    Abstract: A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: August 9, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Brian Smith, Parthasarathy Sriram, Stephane Le Provost
  • Patent number: 8327173
    Abstract: In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: December 4, 2012
    Assignee: Nvidia Corporation
    Inventors: Neil Hendin, Zahid Najam, Stephane Le Provost, Brian Smith
  • Publication number: 20090204834
    Abstract: A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Neil Hendin, Ewa Kubalska, Zahid Najam, Stephane Le Provost, Brian Smith
  • Publication number: 20090204835
    Abstract: In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Applicant: NVIDIA Corporation
    Inventors: Brian Smith, Parthasarathy Sriram, Stephane Le Provost
  • Publication number: 20090201082
    Abstract: A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Brian Smith, Parthasarathy Sriram, Stephane Le Provost
  • Publication number: 20090153211
    Abstract: In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Inventors: Neil Hendin, Zahid Najam, Stephane Le Provost, Brian Smith