Patents by Inventor Stephane Le Tual
Stephane Le Tual has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11005490Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.Type: GrantFiled: July 1, 2020Date of Patent: May 11, 2021Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS SAInventors: Stéphane Le Tual, David Duperray, Jean-Pierre Blanc
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Patent number: 10972097Abstract: In accordance with an embodiment of the present invention, an optical switch includes a photoconductor body including a first edge and an opposite second edge, a first end and an opposite second end. The first edge is configured to receive an electrical input signal and the second edge is configured to deliver an electrical output signal. The photoconductor body is configured to have an electrically ON state that is activated by an optical signal and an electrically OFF state that is activated by an absence of the optical signal. A direction from the first end to the second end defines a longitudinal direction. The direction from the first edge to the second edge defines a first direction that is orthogonal to the longitudinal direction. A first dimension between the first edge and the second edge along the first direction decreases from the first end to the second end.Type: GrantFiled: August 29, 2017Date of Patent: April 6, 2021Assignee: STMICROELECTRONICS SAInventors: Hanae Zegmout, Denis Pache, Stephane Le Tual, Jean-François Roux, Jean-Louis Coutaz
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Patent number: 10917106Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.Type: GrantFiled: December 10, 2019Date of Patent: February 9, 2021Assignees: STMicroelectronics SA, STMicroelectronics (Alps) SASInventors: Stephane Le Tual, Jean-Pierre Blanc, David Duperray
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Publication number: 20210006256Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.Type: ApplicationFiled: July 1, 2020Publication date: January 7, 2021Inventors: Stéphane Le Tual, David Duperray, Jean-Pierre Blanc
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Publication number: 20200350910Abstract: In accordance with an embodiment of the present invention, an optical switch includes a photoconductor body including a first edge and an opposite second edge, a first end and an opposite second end. The first edge is configured to receive an electrical input signal and the second edge is configured to deliver an electrical output signal. The photoconductor body is configured to have an electrically ON state that is activated by an optical signal and an electrically OFF state that is activated by an absence of the optical signal. A direction from the first end to the second end defines a longitudinal direction. The direction from the first edge to the second edge defines a first direction that is orthogonal to the longitudinal direction. A first dimension between the first edge and the second edge along the first direction decreases from the first end to the second end.Type: ApplicationFiled: August 29, 2017Publication date: November 5, 2020Inventors: Hanae Zegmout, Denis Pache, Stephane Le Tual, Jean-François Roux, Jean-Louis Coutaz
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Publication number: 20200212927Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.Type: ApplicationFiled: December 10, 2019Publication date: July 2, 2020Applicants: STMicroelectronics SA, STMicroelectronics (Alps) SASInventors: Stephane LE TUAL, Jean-Pierre BLANC, David DUPERRAY
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Patent number: 10312889Abstract: The present disclosure relates to a device for generating a clock signal including a first photoresistor coupling a capacitive output node to a node receiving a first potential. A second photoresistor couples the capacitive node to a node receiving a second potential. The first and second photoresistors receive the same optical pulses of a mode-locked laser at instants in time offset by a first delay.Type: GrantFiled: May 25, 2017Date of Patent: June 4, 2019Assignee: STMicroelectronics SAInventors: Denis Pache, Stephane Le Tual, Hanae Zegmout
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Patent number: 10305456Abstract: The present disclosure relates to a device for converting an optical pulse to an electronic pulse includes a photoresistor having first and second terminals and being capable of receiving a pulsed laser signal arising from a mode-locked laser source The first terminal is linked to a node for applying a reference potential via a resistive element and a capacitive element connected in parallel. The second terminal is connected to a node for applying a supply potential.Type: GrantFiled: May 25, 2017Date of Patent: May 28, 2019Assignee: STMicroelectronics SAInventors: Hanae Zegmout, Denis Pache, Stephane Le Tual
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Publication number: 20180152180Abstract: The present disclosure relates to a device for generating a clock signal including a first photoresistor coupling a capacitive output node to a node receiving a first potential. A second photoresistor couples the capacitive node to a node receiving a second potential. The first and second photoresistors receive the same optical pulses of a mode-locked laser at instants in time offset by a first delay.Type: ApplicationFiled: May 25, 2017Publication date: May 31, 2018Inventors: Denis Pache, Stephane Le Tual, Hanae Zegmout
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Publication number: 20180152179Abstract: The present disclosure relates to a device for converting an optical pulse to an electronic pulse includes a photoresistor having first and second terminals and being capable of receiving a pulsed laser signal arising from a mode-locked laser source The first terminal is linked to a node for applying a reference potential via a resistive element and a capacitive element connected in parallel. The second terminal is connected to a node for applying a supply potential.Type: ApplicationFiled: May 25, 2017Publication date: May 31, 2018Inventors: Hanae Zegmout, Denis Pache, Stephane Le Tual
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Publication number: 20170288781Abstract: An optical modulator includes an optical waveguide including at least a first PN junction phase shifter and a second PN junction phase shifter. A driver circuit drives operation of the first and second PN junction phase shifters in response to a pulse amplitude modulated (PAM) analog signal having 2n levels. The PAM analog signal is generated by a digital to analog converter that receives an n-bit input signal. In an implementation, the optical waveguide and PN junction phase shifters are formed on a first integrated circuit chip and the driver circuit is formed on a second integrated circuit chip that is stacked on and electrically connected to the first integrated circuit chip.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Jean-Francois Carpentier, Patrick Lemaitre, Jean-Robert Manouvrier, Denis Pache, Stephane Le Tual
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Patent number: 9698815Abstract: A multiplying digital to analog converter includes first and second inputs for receiving first and second differential input signals. A differential amplifier has first and second differential input nodes and first and second differential output nodes. A first capacitor is coupled in series with a first switch between the first differential input node and the first input. The first capacitor is further coupled to at least one reference voltage supply node via one or more further switches. A second capacitor is coupled between the first differential input node and the first differential output node. A third capacitor is coupled between the first differential input node and the first input.Type: GrantFiled: August 16, 2016Date of Patent: July 4, 2017Assignee: STMicroelectronics SAInventors: Mounir Boulemnakher, Stephane Le Tual
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Patent number: 9432008Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.Type: GrantFiled: July 22, 2014Date of Patent: August 30, 2016Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Stéphane Le Tual, Pratap Narayan Singh
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Patent number: 9298666Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.Type: GrantFiled: November 18, 2011Date of Patent: March 29, 2016Assignee: STMicroelectronics SAInventors: Stéphane Le Tual, Pratap Singh
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Patent number: 9000964Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).Type: GrantFiled: June 3, 2014Date of Patent: April 7, 2015Assignees: STMicroelectronics SA, STMicroelectronics International N.V.Inventors: Stéphane Le Tual, Pratap Narayan Singh
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Patent number: 9000963Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.Type: GrantFiled: June 2, 2014Date of Patent: April 7, 2015Assignees: STMicroelectronics SA, STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Stéphane Le Tual
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Publication number: 20150028930Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.Type: ApplicationFiled: July 22, 2014Publication date: January 29, 2015Inventors: Stéphane Le Tual, Pratap Narayan Singh
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Publication number: 20140361915Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Inventors: Stéphane LE TUAL, Pratap Narayan SINGH
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Publication number: 20140361914Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.Type: ApplicationFiled: June 2, 2014Publication date: December 11, 2014Inventors: Pratap Narayan SINGH, Stéphane LE TUAL
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Patent number: 8514123Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.Type: GrantFiled: September 28, 2011Date of Patent: August 20, 2013Assignee: STMicroelectronics S.A.Inventors: Stéphane Le Tual, Mounir Boulemnakher, Pratap Narayan Singh