Abstract: Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating one or several memory locations (46a-d, 47a-b) arranged in accordance with a sequence suitable for said request, processing the requests in accordance with a successive sequence so as to transfer, for each processed request, data from the designated memory location to the data processing circuit, or vice versa, the processing of a request (46) designating memory locations (46a, 46b, 46c, 46d) associated with several banks (A, B, A, B) authorizing a transfer of data between the interface and the memory locations in a sequence which is different from the sequence associated with said request.

Abstract: The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit (20) including a reconstruction circuit (16) for reconstructing pictures from decoded data and an external memory (1) for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller (11) for controlling data exchange between the processing unit and the external memory, a cache memory (17) for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit (14) for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

Abstract: The invention relates to a chip for processing a content, comprising at least a microprocessor. Said chip includes an integrated non-volatile programmable memory for storing protection data and protected data, said protection data being intended to be used for authorizing/denying access to said protected data by said microprocessor under execution of a program. The invention allows to protect program and data dedicated to a chip-integrated conditional-access system and to protect features as external connections and downloaded data directly on the chip.

Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: The invention relates to a secure data processing system including an unscrambling module [DSC] disposed on a dedicated hardware part [HW] of an integrated circuit and intended to unscramble a stream of data [SP] scrambled according to a scrambling key, a module [CM] for calculating an unscrambling key [Kp] disposed on said dedicated hardware part [HW] and intended to manipulate data under the control of a so-called calculation program stored on said dedicated hardware part [HW], a processor [CPU] for in particular controlling the functioning of the unscrambling [DSC] and calculation [CM] modules. Said system also includes a read only memory [SME] disposed on said dedicated hardware part [HW] for storing a secret key [Kp]. Said calculation program includes instructions for prompting said calculation module [CM] to use said secret key [L] and at least one data item [AC[n,p] or Kpc)] coming from outside the secure data processing system, in order to calculate an unscrambling key [Kp].

Abstract: A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).

Abstract: Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:

Abstract: Method of managing access of a plurality of data processing circuits (4, 7) to a common memory (1) comprising several banks (A-D), the memory being connected to one or several circuits (7) for processing ordinary data and to a circuit (4) for processing priority data, the method comprising the steps of:—producing an access demand of the or one of the circuits for processing ordinary data to a bank of the memory;—starting the realization of the demanded access;—subsequently producing an access demand of the circuit for processing priority data to another bank of the memory;—preparing (PRE, ACT), during the realization of the access demanded by the or one of the ordinary data processing circuits, said other bank of the memory;—interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Abstract: A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.