Abstract: A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on

Abstract: A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on

Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analogue signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analogue signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analogue signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analogue signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (?p) differing by a power of two and situated in the vicinity of 2i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract: The invention concerns a dual-polarisation antenna comprising: a microstrip substrate (1) covered, on a first face, with a metallisation (M) and, on a face opposite to the first face, with two microstrip lines; a dielectric resonator (2) having the form of a cylinder of revolution fixed to an etching (4) formed in the substrate, a first end of a first one of the two microstrip lines forming a first port of the antenna and a first end of the second microstrip line forming a second port of the antenna; and an electrically conductive linear element (3) placed in contact with the dielectric resonator and connected to a second end of the first line (L1), via a hole (5) formed in the substrate (1), a second end of the second line (L2) being substantially vertical to the etching.

Abstract: An electronic circuit includes several (at least two) oscillating and/or resonant devices. The circuit uses a measuring device to measure the phase noise of one of the two oscillating/resonant devices. This measuring device is integrated on a chip on which the oscillating/resonant device to be measured is also integrated. The circuits and methods described find application in the area of radiofrequency/high frequency electronics RF/HF, in particular adapted to general public applications in mobile communication systems and/or to metrology.

Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (?p) differing by a power of two and situated in the vicinity of 2i?1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract: An electronic circuit includes several (at least two) oscillating and/or resonant devices. The circuit uses a measuring device to measure the phase noise of one of the two oscillating/resonant devices. This measuring device is integrated on a chip on which said oscillating/resonant device to be measured is also integrated. The circuits and methods described find application in the area of radiofrequency/high frequency electronics RF/HF, in particular adapted to general public applications in mobile communication systems and/or to metrology.