Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: The present description concerns an optical diffuser including a first layer having an electrically-conductive track formed therein, and a second layer, having the first layer resting thereon resting thereon, and having at least two electrically-conductive pillars extending across the entire thickness of the second layer formed therein. The second layer includes at least one first region located under the conductive track comprising no pillar.

Abstract: An optical filter includes a carrier layer made of a first material. A periodic grating of posts is disposed on the carrier layer in a periodic pattern configured by characteristic dimensions. The posts are made of a second material. A layer made of a third material encompasses the periodic grating of posts and covers the carrier layer. The third material has a refractive index that is different from a refractive index of the second material. Characteristic dimensions of the periodic grating of posts are smaller than an interfering wavelength and are configured to selectively reflect light at the interfering wavelength on the periodic grating of posts.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.