Patents by Inventor Stephanie A. Yoshikawa

Stephanie A. Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6054062
    Abstract: A method and apparatus agitates an etchant contained within a bath. A wafer is immersed in a bath containing an etchant that is continuously mixed by release of a gas, preferably nitrogen, into the bath at a sufficient flow rate to agitate the etchant and assure a robust and substantially uniform selective etching process. The apparatus comprises valve assembly that receives gas from a source of gas under pressure and controls the flow rate and release pressure of the gas. In addition, the valve assembly contains an on/off valve that, when turned on, releases gas for a predetermined time period. Accordingly, a single operation of the on/off valve releases gas for the duration of a single selective etching cycle. A dispersion plate receives the gas from the valve assembly for release into the bath. The released gas passes through the baffle distribution plate that distributes the gas throughout the bath.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: April 25, 2000
    Assignee: LSI Logic Corporation
    Inventors: Jeffrey C. Calio, Stephanie A. Yoshikawa, Timothy Hendrix
  • Patent number: 5933757
    Abstract: An etch process selective to cobalt silicide is described for the selective removal of titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, remaining after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide. The first step comprises contacting the substrate with an aqueous mixture of ammonium hydroxide (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) to selectively remove any titanium and/or titanium nitride in preference to the removal of cobalt silicide. The second step comprises contacting the substrate with an aqueous mixture of phosphoric acid (H.sub.3 PO.sub.4), acetic acid (CH.sub.3 COOH), and nitric acid (HNO.sub.3) to selectively remove cobalt and cobalt reaction products (other than cobalt silicide) in preference to the removal of cobalt silicide.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Stephanie A. Yoshikawa, Wilbur G. Catabay
  • Patent number: 5902129
    Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Stephanie A. Yoshikawa, Zhihai Wang, Wilbur G. Catabay