Patents by Inventor Stephanie L. Alter

Stephanie L. Alter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8468478
    Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: June 18, 2013
    Assignee: Agere Systens LLC
    Inventors: Stephanie L. Alter, Kevin D. Drucker, Vishwas Rao, Leon Song
  • Patent number: 7610568
    Abstract: Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned to create a set of valid flops and valid scan chains based on a set of pruning rules. A unified flop database is generated containing physical location and connection information for the new flops and the set of valid flops. A change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops is generated meeting allocation and placement sensitive signal connection rules. The new flops are connected to the selected valid flops allowing design for test requirements to be met.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: October 27, 2009
    Assignee: Agere Systems Inc.
    Inventors: Stephanie L. Alter, Vishwas Rao
  • Publication number: 20080295054
    Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
    Type: Application
    Filed: August 7, 2008
    Publication date: November 27, 2008
    Applicant: Agere Systems Inc.
    Inventors: Stephanie L. Alter, Kevin D. Drucker, Vishwas Rao, Leon Song
  • Patent number: 7424693
    Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: September 9, 2008
    Assignee: Agere Systems Inc.
    Inventors: Stephanie L. Alter, Kevin D. Drucker, Vishwas Rao, Leon Song