Patents by Inventor Stephanie Leanne HILBUN

Stephanie Leanne HILBUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor manufacturing optimization by combining small lots into individual carriers
    Patent number: 8707220
    Abstract: An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Byron Joseph Palla, Stephanie Leanne Hilbun
  • SEMICONDUCTOR MANUFACTURING OPTIMIZATION BY COMBINING SMALL LOTS INTO INDIVIDUAL CARRIERS
    Publication number: 20130344624
    Abstract: An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 26, 2013
    Inventors: Byron Joseph PALLA, Stephanie Leanne HILBUN