Patents by Inventor Stephanie Watts Butler
Stephanie Watts Butler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10431551Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.Type: GrantFiled: January 11, 2018Date of Patent: October 1, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kenneth Michael Butler, Kalyan Chakravarthy Cherukuri, Stephanie Watts Butler, Venkataramanan Kalyanaraman, Hubert Joseph Payne, Yazdi Dinshaw Contractor
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Publication number: 20180130754Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.Type: ApplicationFiled: January 11, 2018Publication date: May 10, 2018Inventors: Kenneth Michael Butler, Kalyan Chakravarthy Cherukuri, Stephanie Watts Butler, Venkataramanan Kalyanaraman, Hubert Joseph Payne, Yazdi Dinshaw Contractor
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Patent number: 9899332Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.Type: GrantFiled: February 18, 2016Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kenneth Michael Butler, Kalyan Chakravarthy Cherukuri, Stephanie Watts Butler, Venkataramanan Kalyanaraman, Hubert Joseph Payne, Yazdi Dinshaw Contractor
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Publication number: 20170243831Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.Type: ApplicationFiled: February 18, 2016Publication date: August 24, 2017Inventors: Kenneth Michael Butler, Kalyan Chakravarthy Cherukuri, Stephanie Watts Butler, Venkataramanan Kalyanaraman, Hubert Joseph Payne, Yazdi Dinshaw Contractor
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Patent number: 8051398Abstract: Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.Type: GrantFiled: December 31, 2007Date of Patent: November 1, 2011Assignee: Texas Instruments IncorporatedInventors: Clive D. Bittlestone, Kenneth M. Butler, Mark E. Mason, Stephanie Watts Butler
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Patent number: 7531398Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.Type: GrantFiled: October 19, 2006Date of Patent: May 12, 2009Assignee: Texas Instruments IncorporatedInventors: Zhibo Zhang, Cloves Rinn Cleavelin, Michael Francis Pas, Stephanie Watts Butler, Mike Watson Goodwin, Satyavolu Srinivas Papa Rao
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Publication number: 20090037854Abstract: Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.Type: ApplicationFiled: December 31, 2007Publication date: February 5, 2009Inventors: Clive D. Bittlestone, Kenneth M. Butler, Mark E. Mason, Stephanie Watts Butler
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Publication number: 20080096338Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Inventors: Zhibo Zhang, Cloves Rinn Cleavelin, Michael Francis Pas, Stephanie Watts Butler, Mike Watson Goodwin, Satyavolu Srinivas Papa Rao
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Patent number: 6812073Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.Type: GrantFiled: December 10, 2002Date of Patent: November 2, 2004Assignee: Texas Instrument IncorporatedInventors: Haowen Bu, Amitabh Jain, Wayne A. Bather, Stephanie Watts Butler
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Patent number: 6787425Abstract: Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.Type: GrantFiled: June 16, 2003Date of Patent: September 7, 2004Assignee: Texas Instruments IncorporatedInventors: Antonio Luis Pacheco Rotondaro, Trace Quentin Hurd, Stephanie Watts Butler, Majid M. Mansoori
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Publication number: 20040110352Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.Type: ApplicationFiled: December 10, 2002Publication date: June 10, 2004Applicant: Texas Instruments IncorporatedInventors: Haowen Bu, Amitabh Jain, Wayne A. Bather, Stephanie Watts Butler
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Publication number: 20040067631Abstract: Seed layer roughness can be reduced in conjunction with formation of a SiGe gate electrode. Surface characteristics of a gate dielectric can be modified, such by use of a nitrogen containing gas, prior to deposition of the seed layer on to the dielectric. The modifications in surface characteristics enable a thin seed layer to be formed overlying the gate dielectric with a reduced roughness relative to many conventional approaches.Type: ApplicationFiled: October 3, 2002Publication date: April 8, 2004Inventors: Haowen Bu, Stephanie Watts Butler, Rajesh Khamankar, Hiroaki Niimi
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Patent number: 5838595Abstract: The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.Type: GrantFiled: November 25, 1996Date of Patent: November 17, 1998Assignee: Texas Instruments, Inc.Inventors: Michael Francis Sullivan, Judith Susan Hirsch, Stephanie Watts Butler, Nicholas John Tovell, Jerry Alan Stefani, Purnendu K. Mozumder, Ulrich H. Wild, Chun-Jen Jason Wang, Robert A. Hartzell