Patents by Inventor Stephanie Wilhelm

Stephanie Wilhelm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods to reduce or prevent strain relaxation on PFET devices and corresponding novel IC products
    Patent number: 10923594
    Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Dirk Utess, Peter Philipp Steinmann, Stephanie Wilhelm
  • METHODS TO REDUCE OR PREVENT STRAIN RELAXATION ON PFET DEVICES AND CORRESPONDING NOVEL IC PRODUCTS
    Publication number: 20200203530
    Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Dirk Utess, Peter Philipp Steinmann, Stephanie Wilhelm