Abstract: For sequencing of power rails, a plurality of switches, which operate independently of each other, are operable to control delivery of power from an input power rail to an output power rail. The delivery of the power is controlled by a control input. A time delay circuit is operable to delay the control input by a time period. An input discrete component, coupled in series with the delay circuit, is configurable to adjust the time period. A fast discharge circuit is enabled to override the time period on a trailing edge of the output power rail. A discharge circuit that is coupled to the output power rail includes an output discrete component, the component being selectable to control a decay rate of the output power rail.

Abstract: For sequencing of power rails, a plurality of switches, which operate independently of each other, are operable to control delivery of power from an input power rail to an output power rail. The delivery of the power is controlled by a control input. A time delay circuit is operable to delay the control input by a time period. An input discrete component, coupled in series with the delay circuit, is configurable to adjust the time period. A fast discharge circuit is enabled to override the time period on a trailing edge of the output power rail. A discharge circuit that is coupled to the output power rail includes an output discrete component, the component being selectable to control a decay rate of the output power rail.

Abstract: An information handling system (“IHS”) including a processor is provided. The IHS also includes an audio input device interface coupled to the processor. Moreover, the IHS includes a voltage regulator coupled to the interface for determining whether an audio input device is coupled to the interface. The voltage regulator also supplies power to the audio input device in response to determining that an audio input device is coupled to the interface.

Abstract: In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Abstract: In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Abstract: A system and method that include reading a first identifier associated with a first audio output device from a memory location, selecting a first set of filter coefficients associated with the first identifier, and providing the first set of filter coefficients to an audio generation module for use with the first audio output device are provided.

Abstract: In a computer system, an apparatus including a power supply system having a voltage regulator and a power supply for supplying an unregulated voltage to the voltage regulator. A memory connector is mounted on the motherboard. The memory connectors is configured to receive a memory module. A memory controller is mounted on the motherboard. A riser card having an edge portion configured to be received by the memory module is removably inserted into the memory connector. A riser card interface is coupled from the riser card to the power supply system and memory switch for enabling an interface-dependent voltage to be established by the voltage regulator and supplied to the memory controller. The interface-dependent voltage is supplied to the riser card through the memory connector and is maintained at a level whereby the memory connector is subjected to an electrical current less than a maximum prescribed current. A voltage modifying device is mounted on the riser card.