Abstract: A master secondary clock system of the analog impulse type consisting of separate motor driven secondary clocks and a master control unit. The secondary clocks can be set at any time by an appropriate signal from the master clock so that even widely scattered secondary clocks can be brought at any time to the correct time. In one disclosed embodiment, the secondary clocks are moved by a series of rapid pulses form the master clock to a predetermined known time, the secondary clocks are brought into registry, the master clock calculates the time disparity between the registration time and the real time, and the secondary clocks are moved in unison to the real time.

Abstract: A master/secondary clock system of the impulse type consisting of stepper motor driven secondary clocks and a master control unit. At five minutes before a predetermined registration time, for example 6:00, the sensor of each secondary clock movement is activated by a reverse polarity signal from the master control unit and a series of reset pulses are thereafter transmitted to the secondary clocks with each secondary clock stopping as the window in its drive train gear moves into alignment with the emitter and detector of its sensor mechanism. After this five minute pulse reset phase to correct clocks that are five or less minutes fast, the master control unit transmits a rapid pulse train so as to quickly move all of the remaining clocks to the 6:00 position with each clock being halted at the 6:00 position by movement of the window of its gear into alignment with the emitter and detector of the sensor mechanism of that clock.