Abstract: A logic power network provided in an application-specific integrated circuit (ASIC). The ASIC includes a central processor. The ASIC also includes at least one intellectual property (IP) core operatively connected with the central processor and having a set of electrical components provided therein. The ASIC also includes a network-on-chip (NOC) operatively connected with the central processor and the at least one IP core. The ASIC also includes a logic power network operatively connected with the central processor, the at least one IP core and the set of electrical components therein, and the NOC. The logic power network is adapted to control power of the at least one IP core and the set of electrical components provided in the at least one IP Core individually and separately.

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.