Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Abstract: Excess signal charge generated in response to optical overload of a charge-coupled sensing region is removed from that region by an antiblooming drain implanted in the substrate of the sensing array. The antiblooming drain is separated from the row of sensing regions by a potential barrier produced by a gate electrode associated with the drain. In fabricating the charge-coupled optical imager, the antiblooming drain is self-aligned with the antiblooming gate electrodes by first providing a pair of spaced-apart antiblooming gate electrodes and implanting the drain region into the substrate using the gate electrodes as a mask.