Abstract: A method of coordinating positioning signaling includes: identifying a first user equipment (UE) served by a base station and a second UE served by the base station, the base station being configured to send a base station positioning signal wirelessly at a plurality of base-station-transmission times; allocating first times to the first UE, for sending first UE positioning signals, and second times to the second UE, for sending second UE positioning signals, at least one of the first times being different from at least one of the second times; sending a first communication to cause the first UE to send at least a respective one of the first UE positioning signals at each of the first times; and sending a second communication to cause the second UE to send at least a respective one of the second UE positioning signals at each of the second times.

Abstract: An external client requests the location of a UE using control plane signaling. The UE sends downlink location measurements, such as Reference Signal Time Differences, for a plurality of base stations (BSs) to a serving BS at a layer 1 or layer 2 protocol level and at first periodic intervals. The UE and the plurality of BSs send additional location measurements, such as receive time-transmission time differences, to the serving BS at second periodic intervals, which are longer than the first periodic intervals. The serving BS uses the additional location measurements and downlink location measurements to determine timing information, such as Real Time Differences, for the plurality of BSs. The serving BS determines the location of the UE using the downlink location measurements and the timing information at the first periodic intervals and sends the location to the external client using user plane signaling to reduce delay.

Abstract: A method may include coupling a device to a host through a connector, receiving, by a host controller, a request for boost power from the device, determining, by the host controller, an amount of surplus power available from one or more power sources arranged to provide power to the device through the connector, and allocating at least a portion of the surplus power to the device as boost power. The method may further include negotiating an amount of the boost power based on the amount of surplus power available from the one or more power sources. The method may further include monitoring a power consumption of the device, and reducing a total power allocation to the device based on the power consumption of the device.

Abstract: A Lightweight Bridge (LWB) is disclosed. The LWB may be a circuit. An endpoint of the LWB that may expose a plurality of Physical Functions (PFs) to a host. A root port of the LWB may connect to a device and determine the PFs and Virtual Functions (VFs) exposed by the device. An Application Layer-Endpoint (APP-EP) and an Application Layer-Root Port (APP-RP) may translate between the PFs exposed by the endpoint and the PFs/VFs exposed by the device. The APP-EP and the APP-RP may implement a mapping between the PFs exposed by the endpoint and the PFs/VFs exposed by the device.

Abstract: A solid state drive (SSD) is disclosed. The SSD may include flash memory to store data and an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a field programmable gate array (FPGA) operative to perform a comparison of a search sequence with a reference sequence, where the reference sequence is stored in the flash memory. The FPGA may: identify a continuous match of atoms between the search sequence and the reference sequence; divide the search sequence into a left portion of the search sequence that includes atoms before the continuous match of atoms in the search sequence, a center portion of the search sequence that includes the continuous match of atoms in the search sequence, and a right portion of the search sequence that includes atoms after the continuous match of atoms in the search sequence; match the left portion of the search sequence with the reference sequence; and match the right portion of the search sequence with the reference sequence.

Abstract: A method is described for producing a component, having a first constructive step in which a support material is applied onto a bearer using a photoelectric print method in the first constructive step to form at least one auxiliary structure, the auxiliary structure having and/or forming intermediate spaces, and having a second constructive step, in which a component material is filled into the intermediate spaces using a further photoelectric print method to form a component structure, the auxiliary structure and the component structure forming a blank segment of the component, the component material being a powder, the powder including composite particles, the composite particles being formed by ceramic and/or metallic core particles that include a polymer 23.

Abstract: An energy efficient film comprising of first and second substrate layers and microstructures positioned between the first and second substrates is provided. The microstructures are positioned between the first and second structures such that a vacuum environment is created between the first and second substrates. In one embodiment, the insulating film includes a first substrate, a second substrate, and a plurality of microstructures positioned between the first substrate and the second substrate, such that a vacuum environment is created between the first and second substrates and within each microstructure cell, individually. Preferably, the plurality of microstructures is a polygonal cellular network positioned between a first transparent substrate and a second transparent substrate. A gasket may be provided on one or both of the first or second substrates. The gasket may also be provided on outer edges of the first and/or the second substrate.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.

Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.

Abstract: A system and method for transmitting stateful data over a highly reliable stateless communications channel between a master device and a slave device is provided. Data that has been transmitted from the master device to the slave device is maintained in a buffer at the master device until the slave devices completes the actions required by commands accompanying the data and reports successful completion of the actions. Should an error occur in the data or processing of the data at the slave device an error message is sent from the slave device to the master device causing the stored transmitted data that has not as yet been acknowledged to be retransmitted to the slave device.

Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

Abstract: The present disclosure is directed to systems and methods for detecting stack-pivot attacks in a processor-based device. Processor circuitry executes one or more applications via sequential execution of instructions on a stack. Stack pivot attacks occur when an attacker takes control of the stack and uses the stack to execute a series of code sections referred to as “gadgets.” A stack-pivot attack detector establishes an allowable processor stack offset change value associated with an application and monitors a processor stack offset change value responsive to an occurrence of a processor stack exchange instruction. A stack-pivot attack is detected when the processor offset change value exceeds the allowable processor stack offset change value. Upon detecting a stack-pivot attack, the stack-pivot detection circuitry causes the selective termination of the application.

Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.

Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.