Patents by Inventor Stephen A. Fischer

Stephen A. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240059908
    Abstract: A coating composition with improved adhesion to a hydrophobic paint primer substrate consisting of a waterborne zwitterionic copolymer coating composition that is biocide-free and zero volatile organic compounds that improves the environmental and sustainability issues of today's toxic marine antifouling coatings.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 22, 2024
    Inventors: Stephen A. Fischer, Sheu-Jane Gallagher, Edward S. Kim, Jennifer Rigney
  • Patent number: 10503517
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20180285559
    Abstract: The present disclosure is directed to systems and methods for detecting stack-pivot attacks in a processor-based device. Processor circuitry executes one or more applications via sequential execution of instructions on a stack. Stack pivot attacks occur when an attacker takes control of the stack and uses the stack to execute a series of code sections referred to as “gadgets.” A stack-pivot attack detector establishes an allowable processor stack offset change value associated with an application and monitors a processor stack offset change value responsive to an occurrence of a processor stack exchange instruction. A stack-pivot attack is detected when the processor offset change value exceeds the allowable processor stack offset change value. Upon detecting a stack-pivot attack, the stack-pivot detection circuitry causes the selective termination of the application.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Rodrigo Branco, Xiaoning Li, David M. Durham, Hongliang Gao, Stephen A. Fischer, Baiju V. Patel
  • Patent number: 10049212
    Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventor: Stephen A. Fischer
  • Patent number: 9946875
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Publication number: 20180060078
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 1, 2018
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V, Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 9874925
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9870044
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9841807
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Publication number: 20170269672
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: December 11, 2015
    Publication date: September 21, 2017
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9727345
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20170206088
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Applicant: lntel Corporation
    Inventors: Stephen A. Fischer, Shekoufeh Qawami, Subramaniam Maiyuran, Salvador Palanca
  • Publication number: 20170116414
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Patent number: 9612835
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Qawami
  • Patent number: 9582663
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Publication number: 20170017297
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9544139
    Abstract: A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: George W. Cox, David Johnston, Martin G. Dixon, Stephen A. Fischer, Jason W. Brandt
  • Patent number: 9383998
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Qawami
  • Patent number: 9342310
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Oawami
  • Publication number: 20160098075
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem