Abstract: A system and method for removing modulated interference (e.g., FSK, MSK, CW) from an input signal demodulates the input signal into a tracking bitstream via a set of phase locked loop (PLL) filters, one PLL filter for each modulated interference component (e.g., signal) known or suspected to be interfering with the input signal. Each PLL filter estimates, based on an estimated modulation frequency and center frequency associated with its target modulated interference component, a peak magnitude, phase, and updated center frequency and, based on these parameters, approximates the target interference component. Each re-created modulated interference component is subtracted from the original input signal to produce an output signal from which the known or suspected modulated interference components have been substantially removed.

Abstract: A receiver apparatus and method for optimized decryption and despreading of a very low frequency (VLF) bitstream is disclosed. In embodiments, the receiver includes antenna elements for receiving a transmission security (TRANSEC) encoded bitstream associated with an uncertainty window size and a spread factor. The receiver includes cryptographic processors that, when the spread factor is sufficiently large, select key section numbers A and data section numbers B based on the window size and spread factor. The cryptographic processors generate an output sequence of correlation windows, each correlation window associated with a symbol of the bitstream, via pipelined sectional mirrored-key convolution based on a key section number A and data section number B chosen to optimize performance (e.g., processor performance, memory performance).

Abstract: A receiver apparatus and method for optimized decryption and despreading of a very low frequency (VLF) bitstream is disclosed. In embodiments, the receiver includes antenna elements for receiving a transmission security (TRANSEC) encoded bitstream associated with an uncertainty window size and a spread factor. The receiver includes cryptographic processors that, when the spread factor is sufficiently large, select key section numbers A and data section numbers B based on the window size and spread factor. The cryptographic processors generate an output sequence of correlation windows, each correlation window associated with a symbol of the bitstream, via pipelined sectional mirrored-key convolution based on a key section number A and data section number B chosen to optimize performance (e.g., processor performance, memory performance).

Abstract: A system may include a receiver, an input digitized data buffer, and a processor. The input digitized data buffer may be configured to accumulate samples of a time domain signal, s(t), from the receiver. The processor may be configured to: remove a confirmed peak from a frequency domain signal, S(f), to produce a corrected frequency domain signal, S?(f); perform an inverse fast Fourier transform to transform the corrected frequency domain signal, S?(f), to a corrected time domain signal, s?(t); perform an inverse window operation on the corrected time domain signal, s?(t), to recover original signal magnitudes; and output digitized data of the corrected time domain signal, s?(t), for signal processing.