Abstract: In a method of forming a matrix addressable display comprising a group of switchable cells, such as liquid crystal cells, having electrodes on each of two parallel plates and thin-film drive transistors disposed on one of the plates, gate resistors are provided by elongate doped polysilicon regions connecting the gate electrodes to address lines. The gate resistors prevent short-circuiting of the address lines in the event of a gate short-circuit occurring in any of the transistors.

Abstract: In a process for depositing a planarising material in spaces between a pattern of regions, such as dye stripes or dots, on a substrate, the planarising material is deposited as a layer over the pattern. The substrate is irradiated, from the reverse side, by a source of radiation, such as UV, to which the pattern material is opaque and to which the planarising material is responsive such that it is rendered insoluble to a particular solvent. The radiation acts on only those parts of the planarising material which are in the spaces. The remainder of the planarising layer is then removed by use of the solvent. Alternatively, or additionally, an ITO or other UV transparent layer may be formed over the pattern and a layer of resist formed thereover. The radiation then passes through the spaces and acts on only the resist areas over the spaces to render them soluble. Those areas and the ITO layer beneath them are then removed by etching, leaving ITO areas accurately aligned with the pattern.