Patents by Inventor Stephen A. Keller
Stephen A. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110841Abstract: Provided are methods and associated apparatus for determining the integrity of a hermetically sealed electronic component. The method and associated apparatus includes the use of an evacuation chamber configured to placing the hermetically sealed electronic component within. The evacuation chamber is then evacuated of atmosphere to then determine an atmospheric pressure evacuation relationship or curve occurring inside the chamber that is, in turn, used to determine the integrity of the hermetically sealed electronic component. Further aspects may include evacuating the chamber through a mass spectrometer coupled to the evacuation chamber for chemical analysis of at least one of the evacuated atmosphere for making further determinations of the integrity of the hermetically sealed electronic component.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Applicant: The United States of America, as represented by the Secretary of the NavyInventors: Brandon Hirsch, Matthew Keller, Stephen Becker, Michael A. Samp
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Publication number: 20240040783Abstract: A Flash IC device having IREAD compensation and a method of fabricating the same. Responsive to determining a gate pattern misalignment, one or more implant conditions for implanting a dopant may be selected to achieve balanced IREAD characteristics between adjacent bitcells of the Flash IC device.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Toan Tran, Stephen A. Keller
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Patent number: 6266661Abstract: An application configuration system including a database, a preprocessed configuration (“PPC”) service processor that communicates with the database, a data exchange system preprocessed configuration application program interface (“DEX PPC API”) that communicates with the PPC service processor, and an application that communicates with the DEX PPC API. A plurality of files having configuration data are stored in the database in a hierarchical arrangement.Type: GrantFiled: November 30, 1998Date of Patent: July 24, 2001Assignee: Platinum Technology IP, Inc.Inventors: Keith Lewish, Duane Boone, Stephen Keller
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Patent number: 6128232Abstract: A method for erasing a non-volatile memory array (18) includes elevating the temperature of the memory array (18) during a ramp-up period. The memory array (18) is irradiated with ultraviolet light at an elevated temperature during an erase period. The temperature of the memory array (18) is incrementally decreased during a ramp-down period.Type: GrantFiled: August 24, 1999Date of Patent: October 3, 2000Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Phat Xuan Mai, Timothy G. Nagel
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Patent number: 6025275Abstract: A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).Type: GrantFiled: December 17, 1997Date of Patent: February 15, 2000Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Quang X. Mai, Charles E. Williams, Stephen A. Keller
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Patent number: 6020640Abstract: A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).Type: GrantFiled: December 17, 1997Date of Patent: February 1, 2000Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Quang X. Mai, Charles E. Williams, Stephen A. Keller
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Platinum silicide Schottky diodes in a titanium-silicided CMOS-based high performance BICMOS process
Patent number: 5672898Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate at which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.Type: GrantFiled: July 25, 1996Date of Patent: September 30, 1997Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah -
Patent number: 5665993Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.Type: GrantFiled: March 26, 1996Date of Patent: September 9, 1997Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah
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Patent number: 5457059Abstract: A method for providing programmable devices in which an insulation layer, such as an oxide (20), TEOS, or the like, is formed during a BiCMOS integrated circuit fabrication process includes forming a first conductor fuse layer (22), for example of TiW or the like, on the insulation layer (20). The fuse layer (22) may then be patterned, and a second insulation layer (23) formed over it. Alternatively, the fuse layer (53) may be left unpatterned and one or more conductor layers (35,36) may be formed over the fuse layer (53). The conductor layer (35,36) is patterned, and the fuse layer (53) thereafter patterned using the conductor layer (35,36) as an etch mask. In either case, contact holes (26) are formed in the insulation layer (20) to regions (14,15) to which contact is desired under the insulation layer (20).Type: GrantFiled: April 28, 1994Date of Patent: October 10, 1995Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah
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Patent number: 5457062Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.Type: GrantFiled: September 2, 1994Date of Patent: October 10, 1995Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah
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Patent number: 5382536Abstract: A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which extends from the D-well region 20 to a first side of the field oxide region 24. A first n doped source/drain region 16 is formed in the D-well region 20 and is spaced from the field oxide region 24. Also, a second n doped source/drain region 18 formed in the silicon layer 14 on a second side of the field oxide region 24. A gate region 26 is formed over the surface of the silicon layer 14 and over a portion of the first source/drain region 16, the D-well region 20, and a portion of the field oxide region 24.Type: GrantFiled: March 15, 1993Date of Patent: January 17, 1995Assignee: Texas Instruments IncorporatedInventors: Satwinder Malhi, Michael C. Smayling, Stephen A. Keller
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Patent number: 5208169Abstract: A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).Type: GrantFiled: June 28, 1991Date of Patent: May 4, 1993Assignee: Texas Instruments IncorporatedInventors: Rajiv R. Shah, Stephen A. Keller
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Patent number: 5047826Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.Type: GrantFiled: June 30, 1989Date of Patent: September 10, 1991Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah
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Patent number: 5023690Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.Type: GrantFiled: February 27, 1990Date of Patent: June 11, 1991Assignee: Texas Instruments IncorporatedInventors: Douglas P. Verret, Michael C. Smayling, Abnash C. Sachdeva, Stephen A. Keller
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Patent number: 4997789Abstract: A method for forming CVD tungsten contacts in a planarized semiconductor body. The method utilizes aluminum as an etch mask and etch stop to prevent etching of underlying layers during contact formation.Type: GrantFiled: October 31, 1988Date of Patent: March 5, 1991Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Piper A. Spry, Martha S. Adams, Ralph G. Harper
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Patent number: 4920072Abstract: Metal interconnects and method for forming same such that an intermediately formed aluminum layer provides an etch stop and etch mask during the tungsten etch back. The method may be used to form tungsten contacts without requiring pre-metal planarization of the semiconductor body.Type: GrantFiled: October 31, 1988Date of Patent: April 24, 1990Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Piper A. Spry, Martha S. Adams, Ralph G. Harper
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Patent number: 4797372Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.Type: GrantFiled: October 24, 1986Date of Patent: January 10, 1989Assignee: Texas Instruments IncorporatedInventors: Douglas P. Verret, Michael C. Smayling, Abnash C. Sachdeva, Stephen A. Keller
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Patent number: D551291Type: GrantFiled: August 25, 2005Date of Patent: September 18, 2007Inventor: Stephen Keller Wagner
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Patent number: D349235Type: GrantFiled: January 28, 1992Date of Patent: August 2, 1994Assignee: The Murus CompanyInventor: C. Stephen Keller