Abstract: Female fiber optic connectors having a weatherproofing collar disposed rearward of a connection port opening that receives a fiber optic plug along with cable assemblies comprising the female fiber optic connector and with methods of making the same. The female fiber optic connectors comprise an actuator such as a rocker latch arm or the like disposed under the weatherproofing collar used for releasing or securing an external fiber optic plug that may be received in the connection port. The weatherproofing collar protects the actuator such as the rocker arm latch and surrounding area from dirt, debris, moisture and the like from ingress into the connector. One or more end caps may be used with the weatherproofing collar. The weatherproofing collar allows for a ruggedized fiber optic connector having a quick connect and release mechanism for the external fiber optic plug connector mated to the female fiber optic connector.

Abstract: An apparatus for maintaining tension of a transmission line in a tubular includes a first clamp segment configured to surround at least a portion of a transmission line and a second clamp segment configured to surround at least a portion of the transmission line. The second clamp segment has a first axial end and a second axial end. The first axial end is configured to contact an axial end of the first clamp segment, such that the first clamp segment and the second clamp segment are configured to apply a force in opposite radial directions to clamp the transmission line with respect to the tubular to lock a position of the transmission line with respect to the tubular.

Abstract: Methods and systems for processing Ethernet data are disclosed and may comprise receiving Ethernet data via a single gigabit Ethernet IP telephone chip. A secure application key may be received from a secure server by an OSM integrated within the gigabit Ethernet IP telephone chip for processing the received Ethernet data. The received Ethernet data may be processed by the gigabit Ethernet IP telephone chip based on the received secure application key. A unique security identifier internal to the single gigabit Ethernet IP telephone chip may be communicated off-chip to the secure server. The unique security identifier may identify the single gigabit Ethernet IP telephone chip. The secure server may authenticate the gigabit Ethernet IP telephone chip based on the unique security identifier internal to the single gigabit Ethernet IP telephone chip, prior to the receiving of the secure application key.

Abstract: An apparatus for maintaining tension of a transmission line in a tubular includes a first clamp segment configured to surround at least a portion of a transmission line and a second clamp segment configured to surround at least a portion of the transmission line. The second clamp segment has a first axial end and a second axial end. The first axial end is configured to contact an axial end of the first clamp segment, such that the first clamp segment and the second clamp segment are configured to apply a force in opposite radial directions to clamp the transmission line with respect to the tubular to lock a position of the transmission line with respect to the tubular.

Abstract: Methods and systems for processing Ethernet data are disclosed and may comprise receiving Ethernet data via a single gigabit Ethernet IP telephone chip. A secure application key may be received from a secure server by an OSM integrated within the gigabit Ethernet IP telephone chip for processing the received Ethernet data. The received Ethernet data may be processed by the gigabit Ethernet IP telephone chip based on the received secure application key. A unique security identifier internal to the single gigabit Ethernet IP telephone chip may be communicated off-chip to the secure server. The unique security identifier may identify the single gigabit Ethernet IP telephone chip. The secure server may authenticate the gigabit Ethernet IP telephone chip based on the unique security identifier internal to the single gigabit Ethernet IP telephone chip, prior to the receiving of the secure application key.

Abstract: A method for processing Ethernet data and may include receiving Ethernet data via at least one Ethernet physical interface transceiver (PHY) integrated within a single Ethernet IP telephone chip. At least one secure application key may be received from a secure server by an on-chip security module (OSM) integrated within the Ethernet IP telephone chip for processing the received Ethernet data. The Ethernet IP telephone chip may be authenticated prior to the processing of the received Ethernet data using a security processor integrated within the OSM. The received Ethernet data may be processed by the Ethernet IP telephone chip based on the received at least one secure application key. The at least one secure application key may be communicated only from the secure server to the Ethernet IP telephone chip. The received Ethernet data may include one or both of video data and/or voice data.

Abstract: A method for processing data may include receiving packetized data via at least one of a plurality of input ports in an Ethernet switch. Each of the plurality of input ports may be partitioned into a plurality of virtual local area network (VLAN) port domains with an assigned port domain identification (ID) for processing 802.1 Class of Service (CoS) priority and Quality of Service (QoS) packetized data. The Ethernet switch may be integrated within a single gigabit Ethernet IP telephone chip, the received packetized data having assigned at least one priority class. One or more bits in at least one of a plurality of registers in the Ethernet switch may be used to filter at least one ingress frame in the packetized data, based on at least one packet header attribute of the at least one ingress frame.

Abstract: A method for processing data may include receiving packetized data via at least one of a plurality of input ports in an Ethernet switch. Each of the plurality of input ports may be partitioned into a plurality of virtual local area network (VLAN) port domains with an assigned port domain identification (ID) for processing 802.1 Class of Service (CoS) priority and Quality of Service (QoS) packetized data. The Ethernet switch may be integrated within a single gigabit Ethernet IP telephone chip, the received packetized data having assigned at least one priority class. One or more bits in at least one of a plurality of registers in the Ethernet switch may be used to filter at least one ingress frame in the packetized data, based on at least one packet header attribute of the at least one ingress frame.

Abstract: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.

Abstract: A method for processing Ethernet data and may include receiving Ethernet data via at least one Ethernet physical interface transceiver (PHY) integrated within a single Ethernet IP telephone chip. At least one secure application key may be received from a secure server by an on-chip security module (OSM) integrated within the Ethernet IP telephone chip for processing the received Ethernet data. The Ethernet IP telephone chip may be authenticated prior to the processing of the received Ethernet data using a security processor integrated within the OSM. The received Ethernet data may be processed by the Ethernet IP telephone chip based on the received at least one secure application key. The at least one secure application key may be communicated only from the secure server to the Ethernet IP telephone chip. The received Ethernet data may include one or both of video data and/or voice data.

Abstract: Methods and systems for processing data are disclosed herein and may comprise processing data via a single gigabit Ethernet IP telephone chip integrated within a gigabit Ethernet IP telephone. At least a portion of the processed data may be communicated to an off-chip DDR memory within the gigabit IP telephone via an on-chip DDR memory interface integrated within the gigabit IP telephone chip. The data may be acquired from the off-chip DDR memory via the DDR memory interface for the processing. A request to process the data may be received by the gigabit Ethernet IP telephone chip. The request for processing the data may comprise a Memory Read command, a Memory Write command, a Memory Write with Reply command, a Memory Swap command, an Input/Output (I/O) Read command, an I/O Write command, and/or an I/O Write with Reply command.

Abstract: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.

Abstract: Methods and systems for processing data are disclosed herein and may comprise receiving packetized data via at least one input port in an 802.1p and 802.1Q QoS compliant Ethernet switch integrated within a single gigabit Ethernet IP telephone chip that processes multiple voice channels. A priority class may be assigned by the 802.1p and 802.1Q compliant QoS Ethernet switch to at least a portion of the received packetized data. The received packetized data may be processed by the 802.1p and 802.1Q QoS compliant Ethernet switch based on the assigned priority class. The priority class may comprise a high priority class and/or a low priority class. If the priority class comprises a high priority class, the portion of the received packetized data may be buffered in a high priority buffer integrated within the 802.1p and 802.1Q QoS compliant Ethernet switch.

Abstract: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.

Abstract: Methods and systems for processing Ethernet data are disclosed and may comprise receiving Ethernet data via a single gigabit Ethernet IP telephone chip. A secure application key may be received from a secure server by an OSM integrated within the gigabit Ethernet IP telephone chip for processing the received Ethernet data. The received Ethernet data may be processed by the gigabit Ethernet IP telephone chip based on the received secure application key. A unique security identifier internal to the single gigabit Ethernet IP telephone chip may be communicated off-chip to the secure server. The unique security identifier may identify the single gigabit Ethernet IP telephone chip. The secure server may authenticate the gigabit Ethernet IP telephone chip based on the unique security identifier internal to the single gigabit Ethernet IP telephone chip, prior to the receiving of the secure application key.

Abstract: Methods, systems, and apparatuses for enabling mobile TV functionality and universal serial bus (USB) functionality are provided. In an example aspect, a mobile television (TV) system includes a mobile TV receiver module and a universal serial bus (USB) interface. The mobile TV receiver module receives a radio frequency (RF) mobile TV signal that includes TV data, and generates a mobile TV data signal that includes the TV data. The USB interface receives the mobile TV data signal, and generates a USB output data signal that includes the TV data. In an aspect, the mobile TV functionality and USB functionality are provided in an integrated circuit chip. In one example, the mobile TV functionality and USB functionality share at least one power supply. In another example, the mobile TV functionality and USB functionality are powered by respective power supplies that are electrically isolated from each other.

Abstract: A system and method for improved performance by a DVB-H receiver is described that allows good Internet Protocol (IP) packets in a Multiprotocol Encapsulation-Forward Error Correction (MPE-FEC) frame to be salvaged even when there are other IP packets in the frame that may have bytes in error after the performance of MPE-FEC operations. To achieve this, the system and method provides a means for ascertaining where IP packets loaded into a memory begin and end in a manner that can be relied upon even when individual bytes of the IP packets, such as certain bytes of the IP packet header used to determine total packet length, may be in error.

Abstract: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.

Abstract: A hardware-implemented video broadcasting receiver is described that is capable handling back-to-back and parallel time slices in an efficient manner, thereby providing improved receiver performance. In one implementation, the hardware-implemented video broadcasting receiver is capable of handling back-to-back time slices of up to 2 Megabits (Mbits) each and, depending upon the MPE-FEC frame size associated with each time slice, up to 8 parallel time slices or up to 4 parallel time slices transmitted back-to-back with 4 other parallel time slices. The hardware-implemented video broadcasting receiver advantageously permits more efficient and flexible use of the available spectrum and increases interoperability with other DVB-H compliant equipment.

Abstract: Methods, systems, and apparatuses for semiconductor wafers and integrated circuit chip packaging techniques are provided. A wafer is fabricated that supports multiple different packaging techniques. The wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer in a central region of each integrated circuit region. A second plurality of terminals is formed on the surface of the wafer in a peripheral region of each integrated circuit region. For each integrated circuit region, each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. The integrated circuit regions can be separated into chips that can be packaged in multiple ways. In an aspect, a wafer may be fabricated that supports wire-bond packaging or wafer level ball grid array (WLBGA) packaging for a common chip/die configuration of the wafer.