Patents by Inventor Stephen A. Murphy

Stephen A. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711438
    Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: July 18, 2017
    Assignee: STATS ChipPAC, Pte. Ltd.
    Inventors: Li-Jen Lin, Stephen A. Murphy, Wei Sun
  • Publication number: 20140264850
    Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 18, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Li-Jen Lin, Stephen A. Murphy, Wei Sun
  • Patent number: 8759209
    Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: June 24, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Li-Jen Lin, Stephen A. Murphy, Wei Sun
  • Patent number: 8309451
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: November 13, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh
  • Publication number: 20120261817
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 18, 2012
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh
  • Publication number: 20110233766
    Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.
    Type: Application
    Filed: February 17, 2011
    Publication date: September 29, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Lin-Jen Lin, Stephen A. Murphy, Wei Sun
  • Publication number: 20100117230
    Abstract: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Rajendra D. Pendse, Stephen A. Murphy
  • Publication number: 20090250814
    Abstract: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 8, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Rajendra D. Pendse, Stephen A. Murphy
  • Publication number: 20090178727
    Abstract: A combination water conservation apparatus a container system placed to collect condensate from an air conditioner window unit or central unit. The container system may optionally comprise one or two containers with the single container system recovering water and retaining a first selected reserve quantity while dispensing excess/overflow water to a watering bucket for use by transport to a selected area for watering. The watering bucket has a lid with a spout and water input/air input hole for filling via a funnel, or for relieving vacuum during pouring. If a second container is utilized, it receives the excess/overflow from the first container and dispenses its excess/overflow to the watering bucket. A reserve quantity is retained in each of the containers, and the reserve is selected by placement of a spout at a height selected to retain the chosen reserve quantity of water.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Inventor: Stephen A. Murphy
  • Publication number: 20090032975
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh
  • Patent number: 5998242
    Abstract: A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: December 7, 1999
    Assignee: LSI Logic Corporation
    Inventors: Galen C. Kirkpatrick, Manickam Thavarajah, Sunil A. Patel, Stephen A. Murphy